AD9957SLASHPCBZ datasheet(40/60 Pages) AD

40 / 60 page

AD9957

Rev. 0 | Page 40 of 60

LVDS

RECEIVER

PROGAMMABLE

DELAY

INTERNAL

CLOCKS

CLOCK

STATE

SYNC STATE

PRESET VALUE

SYNC PULSE

SYSCLK

SETUP AND HOLD

VALIDATION

D1 Q1

LOAD

DELAYED SYNC-IN SIGNAL

SYNC

RECEIVER

DELAY

SYNC

RECEIVER

ENABLE

SYNC_SMP_ERR

SYNC_IN

RISING EDGE

DETECTOR

AND

STROBE

GENERATOR

SYNC

TIMING

VALIDATION

DISABLE

SYNC

VALIDATION

DELAY

CLOCK

GENERATOR

Figure 56. Sync Receiver

CLOCK

SOURCE

SYNC

OUT

REF_CLK

AD9957

NUMBER 1

MASTER DEVICE

FPGA

DATA

FPGA

DATA

FPGA

DATA

EDGE

ALIGNED

AT REF_CLK

INPUTS.

EDGE

ALIGNED

AT SYNC_IN

INPUTS.

SYNC

OUT

REF_CLK

AD9957

NUMBER 2

SYNC

OUT

REF_CLK

AD9957

NUMBER 3

(FOR EXAMPLE AD951x)

CLOCK DISTRIBUTION

AND

DELAY EQUALIZATION

SYNCHRONIZATION

DISTRIBUTION AND

DELAY EQUALIZATION

(FOR EXAMPLE AD951x)

Figure 57. Multichip Synchronization Example

The sync receiver accepts a periodic clock signal at the

SYNC_IN pins. This signal is assumed to originate from an

LVDS-compatible driver. The user can delay the SYNC_IN

signal in steps of ~150 ps by programming the 5-bit sync

receiver delay word in the multichip sync register. For

clarification, the signal at the output of the programmable delay

is referred to as the delayed sync-in signal.

The edge detection logic generates a synchronization pulse

having a duration of one SYSCLK cycle with a repetition rate

equal to the frequency of the signal applied to the SYNC_IN

pins. The sync pulse is generated as a result of sampling the

rising edge of the delayed sync-in signal with the rising edge of

the local SYSCLK. The synchronization pulse is routed to the

internal clock generator, which behaves as a presettable counter

clocked at the SYSCLK rate. The sync pulse presets the counter

to a predefined state (programmable via the 6-bit sync state

preset value word in the multichip sync register). The predefined

state is only active for a single SYSCLK cycle, after which the

clock generator resumes cycling through its state sequence at

the SYSCLK rate. This unique state presetting mechanism gives

the user the flexibility to synchronize devices with specific

relative clock state offsets (by assigning a different sync state

preset value word to each device).

Multiple device synchronization is accomplished by providing

each AD9957 with a SYNC_IN signal that is edge aligned across

all the devices. If the SYNC_IN signal is edge aligned at all devices,

and all devices have the same sync receiver delay and sync state

preset value, then they all have matching clock states (that is,

they are synchronized). This concept is shown in Figure 57 in

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