AD9957SLASHPCBZ datasheet(50/60 Pages) AD

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AD9957

Rev. 0 | Page 50 of 60

Control Function Register 1 (CFR1)

Address 0x00, four bytes are assigned to this register.

Table 18. Bit Descriptions for CFR1 Register

Bit

No.

Mnemonic

Description

0: disables RAM playback functionality (default).

RAM Enable

1: enables RAM playback functionality.

30:20

Not Available

Ineffective unless Bit 31 = 1.

0: RAM playback data routed to baseband scaling multipliers (default).

RAM Playback

Destination

1: RAM playback data routed to baseband I/Q data path.

27:26

Not Available

00: quadrature modulation mode (default).

01: single tone mode.

25:24

Operating Mode

1x: interpolating DAC mode.

Ineffective unless Bits<9:8> = 10b.

0: OSK pin inoperative (default).

Manual OSK

External Control

1: OSK pin enabled for manual OSK control (see the Output Shift Keying (OSK) section).

0: inverse sinc filter bypassed (default).

Inverse Sinc Filter

Enable

1: inverse sinc filter active.

This bit is automatically cleared by the serial I/O port controller. This operation requires several internal clock

cycles to complete, during which time the data supplied to the CCI input by the baseband signal chain is

ignored. The inputs are forced to all zeros to flush the CCI data path, after which the CCI accumulators are reset.

0: normal operation of the CCI filter (default).

Clear CCI

1: initiates an asynchronous reset of the accumulators in the CCI filter.

20:17

Not Available

Ineffective unless Bits<25:24> = 01b.

0: cosine output of the DDS is selected (default).

Select DDS Sine

Output

1: sine output of the DDS is selected.

15:14

Not Available

0: normal operation of the DDS phase accumulator (default).

Autoclear Phase

Accumulator

1: synchronously resets the DDS phase accumulator any time I/O_UPDATE is asserted or a profile

change occurs.

Not Available

0: normal operation of the DDS phase accumulator (default).

Clear Phase

Accumulator

1: asynchronous, static reset of the DDS phase accumulator.

0: normal operation of the OSK amplitude ramp rate timer (default).

Load ARR @ I/O

Update

1: OSK amplitude ramp rate timer reloaded any time I/O_UPDATE is asserted or a profile change occurs.

0: OSK disabled (default).

OSK (Output Shift

Keying) Enable

1: OSK enabled.

Ineffective unless Bit 9 = 1.

0: manual OSK enabled (default).

Select Auto-OSK

1: automatic OSK enabled.

This bit is effective without the need for an I/O update.

0: clock signals to the digital core are active (default).

Digital Power-

Down

1: clock signals to the digital core are disabled.

0: DAC clock signals and bias circuits are active (default).

DAC Power-Down

1: DAC clock signals and bias circuits are disabled.

This bit is effective without the need for an I/O update.

0: REFCLK input circuits and PLL are active (default).

REFCLK Input

Power-Down

1: REFCLK input circuits and PLL are disabled.

0: auxiliary DAC clock signals and bias circuits are active (default).

Auxiliary DAC

Power-Down

1: auxiliary DAC clock signals and bias circuits are disabled.

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