AD9910SLASHPCBZ datasheet(18/60 Pages) AD

18 / 60 page

AD9910

Rev. 0 | Page 18 of 60

DIGITAL RAMP MODULATION MODE

In digital ramp modulation mode (Figure 24), the modulated

DDS signal control parameter is supplied directly from the

digital ramp generator (DRG). The ramp generation parameters

are controlled through the serial I/O port.

The ramp generation parameters allow the user to control both

the rising and falling slopes of the ramp. The upper and lower

boundaries of the ramp, the step size and step rate of the rising

portion of the ramp, and the step size and step rate of the falling

portion of the ramp are all programmable.

The ramp is digitally generated with 32-bit output resolution.

The 32-bit output of the DRG can be programmed to represent

frequency, phase, or amplitude. When programmed to represent

frequency, all 32 bits are used. However, when programmed to

represent phase or amplitude, only the 16 MSBs or 14 MSBs,

respectively, are used.

The ramp direction (rising or falling) is externally controlled by

the DRCTL pin. An additional pin (DRHOLD) allows the user

to suspend the ramp generator in its present state.

PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE

I/O_UPDATE

RAM

POWER

DOWN

CONTROL

DAC_RSET

IOUT

TxENABLE

DAC FSC

OSK

INVERSE

SINC

FILTER

CLOCK

AMPLITUDE (A)

FREQUENCY (ω)

PHASE (θ)

DIGITAL

RAMP

GENERATOR

DAC FSC

MULTICHIP

SYNCHRONIZATION

SYSCLK

PLL

÷2

REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMING AND

CONTROL

AD9910

PROGRAMMING

REGISTERS

OUTPUT

SHIFT

KEYING

DATA

ROUTE

AND

PARTITION

CONTROL

INTERNAL CLOCK TIMING

AND CONTROL

Acos (ωt+θ)

Asin (ωt+θ)

DDS

AUX

DAC

8-BIT

DAC

14-BIT

RAM_SWP_OVR

DRCTL

DRHOLD

DROVER

Figure 24. Digital Ramp Modulation Mode

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