AD9910SLASHPCBZ datasheet(27/60 Pages) AD

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AD9910

Rev. 0 | Page 27 of 60

The step interval is controlled by a 16-bit programmable timer

that is clocked at a rate of ¼ fSYSCLK. The period of the timer sets

the time interval between amplitude steps. The step time interval

(Δt) is given by

SYSCLK

Δ =

where M is the 16-bit number stored in the amplitude ramp rate

(ARR) portion of the ASF register. For example, if fSYSCLK =

750 MHz and M = 23218 (0x5AB2), then Δt ≈ 123.8293 μs.

The output of the OSK function is a 14-bit unsigned data bus

that controls the amplitude parameter of the DDS (as long as

the OSK enable bit is set). When the OSK pin is set, the OSK

output value starts at 0 (zero) and increments by the pro-

grammed amplitude step size until it reaches the programmed

maximum amplitude value. When the OSK pin is cleared, the

OSK output starts at its present value and decrements by the

programmed amplitude step size until it reaches 0 (zero).

The OSK output does not necessarily attain the maximum

amplitude value if the OSK pin is switched to Logic 0 before the

maximum value is reached. Nor does the OSK output necessarily

reach a value of zero if the OSK pin is switched to Logic 1

before the zero value is reached.

The OSK output is initialized to 0 (zero) at power-up and reset

whenever the OSK enable bit or the select auto OSK bit is cleared.

The amplitude step size of the OSK output is set by the amplitude

step size bits in the ASF register according to Table 10. The step

size refers to the LSB weight of the 14-bit OSK output. Regardless

of the programmed step size, the OSK output does not exceed

the maximum amplitude value programmed into the ASF

Table 10. OSK Amplitude Step Size

ASF<1:0>

Amplitude Step Size

As mentioned previously, a 16-bit programmable timer controls the

step interval. Normally, this timer is loaded with the programmed

timing value whenever the timer expires, initiating a new timing

cycle. However, there are three events that can cause reloading of

the timer to have its timing value reloaded prior to the timer

expiring. One such event is when the select auto OSK bit is

transitioned from cleared to set followed by an I/O update. A

second such event is a change of state in the OSK pin. The third is

dependent on the status of the Load ARR @ I/O Update bit. If this

bit is cleared, then no action occurs, otherwise, when the

I/O_UPDATE pin is asserted (or a profile change occurs), the timer

is reset to its initial starting point.

DIGITAL RAMP GENERATOR (DRG)

DRG Overview

To sweep phase, frequency, or amplitude from a defined start

point to a defined endpoint, a completely digital, digital ramp

generator is included in the AD9910. The DRG makes use of

nine control register bits, three external pins, two 64-bit

registers, and one 32-bit register (see Figure 37).

DIGITAL RAMP LIMIT REGISTER

DDS CLOCK

DIGITAL RAMP RATE REGISTER

DIGITAL RAMP STEP REGISTER

TO DDS

SIGNAL

CONTROL

PARAMETER

DIGITAL RAMP ENABLE

DROVER PIN ACTIVE

LOAD LRR AT I/O_UPDATE

CLEAR DIGITAL

RAMP ACCUMULATOR

AUTOCLEAR DIGITAL

RAMP ACCUMULATOR

DIGITAL RAMP DESTINATION

DIGITAL RAMP NO-DWELL

DIGITAL

RAMP

GENERATOR

Figure 37. Digital Ramp Block Diagram

The primary control for the DRG is the digital ramp enable bit.

When disabled, the other DRG input controls are ignored and the

internal clocks are shut down to conserve power.

The output of the DRG is a 32-bit unsigned data bus that can be

routed to any one of the three DDS signal control parameters, as

controlled by the two digital ramp destination bits in Control

Function Register 2 according to Table 11. The 32-bit output

bus is MSB-aligned with the 32-bit frequency parameter, the

16-bit phase parameter, or the 14-bit amplitude parameter, as

defined by the destination bits. When the destination is phase

or amplitude, the unused LSBs are ignored.

Table 11. Digital Ramp Destination

Digital Ramp

Destination Bits

CFR2<21:20>

DDS signal

Control

Parameter

Bits Assigned to

DDS Parameter

Frequency

31:0

Phase

31:16

1x1

Amplitude

31:18

1 x = don’t care.

The ramp characteristics of the DRG are fully programmable. This

includes the upper and lower ramp limits, and independent control

of the step size and step rate for both the positive and negative slope

characteristics of the ramp. A detailed block diagram of the DRG

appears in Figure 38.

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