AD9910SLASHPCBZ datasheet(58/60 Pages) AD

58 / 60 page

AD9910

Rev. 0 | Page 58 of 60

Multichip Sync Register

Address 0x0A, 4 bytes are assigned to this register.

Table 25. Multichip Sync Register

Bit(s)

Descriptor

Explanation

31:28

Sync Validation Delay

This 4-bit number sets the timing skew (in ~150 ps increments) between SYSCLK and the

delayed sync-in signal for the sync validation block in the sync receiver. Default is 00002.

Sync Receiver Enable

0 = synchronization clock receiver disabled (default).

1 = synchronization clock receiver enabled.

Sync Generator Enable

0 = synchronization clock generator disabled (default).

1 = synchronization clock generator enabled.

Sync Generator Polarity

0 = synchronization clock generator coincident with the rising edge of SYSCLK (default).

1 = synchronization clock generator coincident with the falling edge of SYSCLK.

Not Available

23:18

Sync State Preset Value

This 6-bit number is the state that the internal clock generator assumes when it receives a

sync pulse. Default is 0000002.

17:16

Not Available

15:11

Output Sync Generator

Delay

This 5-bit number sets the output delay (in ~150 ps increments) of the sync generator.

Default is 000002.

10:8

Not Available

7:3

Input Sync Receiver Delay

This 5-bit number sets the input delay (in ~150 ps increments) of the sync receiver. Default

is 000002.

2:0

Not Available

Digital Ramp Limit Register

Address 0x0B, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)

section for details.

Table 26. Bit Descriptions for Digital Ramp Limit Register

Bit(s)

Descriptor

Explanation

63:32

Digital Ramp Upper Limit

32-bit digital ramp upper limit value.

31:0

Digital Ramp Lower Limit

32-bit digital ramp lower limit value.

Digital Ramp Step Size Register

Address 0x0C, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)

section for details.

Table 27. Bit Descriptions for Digital Ramp Step Size Register

Bit(s)

Descriptor

Explanation

63:32

Digital Ramp Decrement

Step Size

32-bit digital ramp decrement step size value.

31:0

Digital Ramp Increment

Step Size

32-bit digital ramp increment step size value.

Digital Ramp Rate Register

Address 0x0D, 4 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)

section for details.

Table 28. Bit Descriptions for Digital Ramp Rate Register

Bit(s)

Descriptor

Explanation

31:16

Digital Ramp Negative

Slope Rate

16-bit digital ramp negative slope value that defines the time interval between decrement

values.

15:0

Digital Ramp Positive Slope

Rate

16-bit digital ramp positive slope value that defines the time interval between increment

values.

AD9910/PCBZ датащи(PDF) 58 Page - Analog Devices

AD9910/PCBZ датащи(HTML) 58 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL