AD9910SLASHPCBZ datasheet(30/60 Pages) AD

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AD9910

Rev. 0 | Page 30 of 60

DRG OUTPUT

LOWER LIMIT

UPPER LIMIT

DRCTL

DRHOLD

AUTOCLEAR DIGITAL

RAMP ACCUMULATOR

CLEAR DIGITAL

RAMP ACCUMULATOR

I/O_UPDATE

POSITIVE

STEP SIZE

NEGATIVE

STEP SIZE

P DDS CLOCK CYCLES

N DDS CLOCK CYCLES

1 DDS CLOCK CYCLE

DIGITAL RAMP ENABLE

DROVER

–Δ

+Δ

Figure 39. Normal Ramp Generation

Event 1—The digital ramp enable bit is set, which has no affect

on the DRG because the bit is not effective until an I/O update.

Event 2—An I/O update registers the enable bit. If DRCTL = 1

is in effect at this time (gray portion of DRCTL trace), then the

DRG output immediately begins a positive slope (gray portion

of DRG output trace). Otherwise, if DRCTL = 0, the DRG

output is initialized to the lower limit.

Event 3—DRCTL transitions to a Logic 1 to initiate a positive

slope at the DRG output. In this example, the DRCTL pin is

held long enough to cause the DRG to reach its programmed

upper limit. The DRG remains at the upper limit until the ramp

accumulator is cleared, DRCTL = 0, or the upper limit is

reprogrammed to a higher value. In the last case, the DRG

immediately resumes its previous positive slope profile.

Event 4—DRCTL transitions to a Logic 0 to initiate a negative

slope at the DRG output. In this example, the DRCTL pin is

held long enough to cause the DRG to reach its programmed

lower limit. The DRG remains at the lower limit until DRCTL = 1,

or the lower limit is reprogrammed to a lower value. In the

latter case, the DRG immediately resumes its previous negative

slope profile.

Event 5—DRCTL transitions to a Logic 1 for the second time,

initiating a second positive slope.

Event 6—The positive slope profile is interrupted by DRHOLD

transitioning to a Logic 1. This stalls the ramp accumulator and

freezes the DRG output at its last value.

Event 7—DRCTL transitions to a Logic 0, releasing the ramp

accumulator and reinstating the previous positive slope profile.

Event 8—The clear digital ramp accumulator bit is set, which

has no affect on the DRG because the bit is not effective until an

I/O update.

Event 9—An I/O update registers that the clear digital ramp

accumulator bit is set, resetting the ramp accumulator and

forcing the DRG output to the programmed lower limit. The

DRG output remains at the lower limit until the clear condition

is removed.

Event 10—The clear digital ramp accumulator bit is cleared,

which has no affect on the DRG because the bit is not effective

until an I/O update.

Event 11—An I/O update registers that the clear digital ramp

accumulator bit is cleared, releasing the ramp accumulator and

the previous positive slope profile restarts.

Event 12—The autoclear digital ramp accumulator bit is set,

which has no affect on the DRG because the bit is not effective

until an I/O update.

Event 13—An I/O update registers that the autoclear digital

ramp accumulator bit is set, resetting the ramp accumulator.

However, with an automatic clear, the ramp accumulator is only

held reset for a single DDS clock cycle. This forces the DRG

output to the lower limit, but the ramp accumulator is

immediately made available for normal operation. In this

example, the DRCTL pin remains a Logic 1, so the DRG output

restarts the previous positive ramp profile.

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