AD9910SLASHPCBZ datasheet(40/60 Pages) AD

40 / 60 page

AD9910

Rev. 0 | Page 40 of 60

WAVEFORM START ADDRESS

WAVEFORM END ADDRESS

RAM ADRESS

RAM_SWP_OVER

I/O_UPDATE

M DDS CLOCK CYCLES

Figure 48. Continuous Recirculate Timing Diagram

RAM Continuous Recirculate Mode

The continuous recirculate mode mimics the ramp up mode,

except that when the state machine reaches the waveform end

address, the next timeout of the internal timer causes the state

machine to jump to the waveform start address. The waveform

repeats until an I/O update or profile change.

The no-dwell high bit is ignored in this mode.

A profile pin state change aborts the current waveform and the

newly selected RAM profile is used to initiate a new waveform.

The RAM_SWP_OVR pin pulses high for two DDS clock cycles

when the state machine reaches the waveform end address.

Continuous recirculate mode is graphically represented in

Figure 48. The circled numbers indicate specific events as

follows:

Event 1—An I/O update or profile change occurs. This event

initializes the state machine to the waveform start address and

sets the RAM_SWP_OVR pin to Logic 0.

Event 2—The state machine reaches the waveform end address

value for the selected profile. The RAM_SWP_OVR pin toggles

to Logic 1 for two DDS clock cycles.

Event 3—The state machine switches to the waveform start

address and continues to increment the address counter.

Event 4—The state machine again reaches the waveform end

address value for the selected profile and the RAM_SWP_OVR

pin toggles to Logic 1 for two DDS clock cycles.

Event 5—The state machine switches to the waveform start

address and continues to increment the address counter.

Event 4 and Event 5—These events repeat until an I/O update

or change in profile.

AD9910/PCBZ датащи(PDF) 40 Page - Analog Devices