AD9910SLASHPCBZ datasheet(31/60 Pages) AD

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AD9910

Rev. 0 | Page 31 of 60

No-Dwell Ramp Generation

The two no-dwell bits in Control Function Register 2 add to the

flexibility of the DRG capabilities. During normal ramp generation,

when the DRG output reaches the programmed upper or lower

limit, it simply remains at the limit until the operating parameters

dictate otherwise. However, during no-dwell operation, the DRG

output does not necessarily remain at the limit. For example, if the

digital ramp no-dwell high bit is set, when the DRG reaches the

upper limit it automatically (and immediately) snaps to the lower

limit (that is, it does not ramp back to the lower limit, it jumps to

the lower limit). Likewise, when the digital ramp no-dwell low bit

is set, when the DRG reaches the lower limit it automatically (and

immediately) snaps to the upper limit.

During no-dwell operation, the DRCTL pin is monitored for state

transitions only, that is, the static logic level is immaterial.

During no-dwell high operation, a positive transition of the

DRCTL pin initiates a positive slope ramp, which continues

uninterrupted (regardless of any further activity on the DRCTL

pin) until the upper limit is reached.

During no-dwell low operation, a negative transition of the DRCTL

pin initiates a negative slope ramp, which continues uninterrupted

(regardless of any further activity on the DRCTL pin) until the

lower limit is reached.

Setting both no-dwell bits invokes a continuous ramping mode

of operation. That is, the DRG output automatically oscillates

between the two limits using the programmed slope parameters.

Furthermore, the function of the DRCTL pin is slightly different.

Instead of controlling the initiation of the ramp sequence, it

only serves to change the direction of the ramp. That is, if the

DRG output is in the midst of a positive slope and DRCTL pin

transitions from Logic 1 to Logic 0, then the DRG immediately

switches to the negative slope parameters and resumes oscilla-

tion between the limits. Likewise, if the DRG output is in the

midst of a negative slope and the DRCTL pin transitions from

Logic 0 to Logic 1, the DRG immediately switches to the positive

slope parameters and resumes oscillation between the limits.

When both no-dwell bits are set, the DROVER signal produces a

positive pulse (two cycles of the DDS clock) each time the DRG

output reaches either of the programmed limits (assuming that the

DROVER pin active bit is set).

A no-dwell high DRG output waveform is shown in Figure 40.

The waveform diagram assumes that the digital ramp no-dwell

high bit is set and has been registered by an I/O update. The

status of the DROVER pin is also shown with the assumption

that the DROVER pin active bit has been set.

UPPER LIMIT

P DDS CLOCK CYCLES

DRG OUTPUT

LOWER LIMIT

DRCTL

POSITIVE

STEP SIZE

DROVER

+Δ

Figure 40. No-Dwell High Ramp Generation

The circled numbers indicate specific events, which are explained

as follows:

Event 1—Indicates the instant that an I/O update registers that the

digital ramp enable bit has been set.

Event 2—DRCTL transitions to a Logic 1, initiating a positive

slope at the DRG output.

Event 3—DRCTL transition to a Logic 0, which has no effect on

the DRG output.

Event 4—Because the digital ramp no-dwell high bit is set, the

moment that the DRG output reaches the upper limit it immedi-

ately switches to the lower limit, where it remains until the next

Logic 0 to Logic 1 transition of DRCTL.

Event 5—DRCTL transitions from Logic 0 to Logic 1, which

restarts at positive slope ramp.

Event 6 and Event 7—DRCTL transitions are ignored until the

DRG output reaches the programmed upper limit.

Event 8—Because the digital ramp no-dwell high bit is set, the

moment that the DRG output reaches the upper limit it

immediately switches to the lower limit, where it remains until

the next Logic 0 to Logic 1 transition of DRCTL.

Operation with the digital ramp no-dwell low bit set (instead of the

digital ramp no-dwell high bit) is similar, except that the DRG

output ramps in the negative direction on a Logic 1 to Logic 0

transition of DRCTL and jumps to the upper limit upon reaching

the lower limit.

DROVER Pin

The DROVER pin provides an external signal to indicate the status

of the DRG. The functionality of this pin is controlled by the

DROVER pin active bit. When this bit is cleared (default), the

DROVER pin is always Logic 0 regardless of the status of the DRG.

When this bit is set, the DROVER pin logic level depends on the

status of the DRG. Specifically, when the DRG output is at either of

the programmed limits, the DROVER pin is Logic 1, otherwise, it is

Logic 0. In the special case of both no-dwell bits set, the DROVER

pin pulses positive for two DDS clock cycles each time the DRG

output reaches either of the programmed limits.

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