ST10F276 datasheet(173/229 Pages) STMICROELECTRONICS

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ST10F276

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When CAN1, CAN2, RTC, XASC, XSSC, I2C, XPWM and the XBUS Additional Features are

all disabled via XPERCON setting, then any access in the address range 00’E800h -

00’EFFFh is directed to external memory interface, using the BUSCONx register

corresponding to the address matching ADDRSELx register. All pins used for X-Peripherals

can be used as General Purpose I/O whenever the related module is not enabled.

XRTCEN

RTC enable

‘0’: Accesses to the on-chip RTC module are disabled, external access performed.

Address range 00’ED00h-00’EDFF is directed to external memory only if

CAN1EN, CAN2EN, XASCEN, XSSCEN, XI2CEN, XPWMEN and XMISCEN are

‘0’ also.

‘1’: The on-chip RTC module is enabled and can be accessed.

XPWMEN

XPWM enable

‘0’: Accesses to the on-chip XPWM module are disabled, external access

performed. Address range 00’EC00h-00’ECFF is directed to external memory only

if CAN1EN, CAN2EN, XASCEN, XSSCEN, XI2CEN, XRTCEN and XMISCEN are

‘0’ also.

‘1’: The on-chip XPWM module is enabled and can be accessed.

XFLASHEN

XFlash enable bit

‘0’: Accesses to the on-chip XFlash and Flash registers are disabled, external

access performed. Address range 09’0000h-0E’FFFFh is directed to external

memory only if XRAM2EN is ‘0’ also.

‘1’: The on-chip XFlash is enabled and can be accessed.

XASCEN

XASC enable bit

‘0’: Accesses to the on-chip XASC are disabled, external access performed.

Address range 00’E900h-00’E9FFh is directed to external memory only if

CAN1EN, CAN2EN, XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are

‘0’ also.

‘1’: The on-chip XASC is enabled and can be accessed.

XSSCEN

XSSC enable bit

‘0’: Accesses to the on-chip XSSC are disabled, external access performed.

Address range 00’E800h-00’E8FFh is directed to external memory only if

CAN1EN, CAN2EN, XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are

‘0’ also.

‘1’: The on-chip XSSC is enabled and can be accessed.

XI2CEN

I2C enable bit

‘0’: Accesses to the on-chip I2C are disabled, external access performed. Address

range 00’EA00h-00’EAFFh is directed to external memory only if CAN1EN,

CAN2EN, XRTCEN, XASCEN, XSSCEN, XPWMEN and XMISCEN are ‘0’ also.

‘1’: The on-chip I2C is enabled and can be accessed.

XMISCEN

XBUS additional features enable bit

‘0’: Accesses to the Additional Miscellaneous Features is disabled. Address range

00’EB00h-00’EBFFh is directed to external memory only if CAN1EN, CAN2EN,

XRTCEN, XASCEN, XSSCEN, XPWMEN and XI2CEN are ‘0’ also.

‘1’: The Additional Features are enabled and can be accessed.

Table 84.

ESFR description (continued)

Bit

Function

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