ST10F276 datasheet(28/229 Pages) STMICROELECTRONICS

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Internal Flash memory

ST10F276

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Bank, or from the other module or again from another memory (internal RAM or external

memory).

Note:

During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the

Flash Control Registers.

4.3.1

Power supply drop

If during a write operation the internal low voltage supply drops below a certain internal

voltage threshold, any write operation running is suddenly interrupted and the modules are

reset to Read mode. At following Power-on, an interrupted Flash write operation must be

repeated.

4.4

Registers description

4.4.1

Flash control register 0 low

The Flash control register 0 low (FCR0L) together with the Flash control register 0 high

(FCR0H) is used to enable and to monitor all the write operations for both the Flash

modules. The user has no access in write mode to the test-Flash (B0TF). Besides, test-

Flash block is seen by the user in Bootstrap mode only.

FCR0L (0x0E 0000)

FCR

Reset value: 0000h

987

65432

reserved

BSY1 BSY0 LOCK res. BSY3 BSY2 res.

RRR

Table 6.

Flash control register 0 low

Bit

Function

BSY(3:2)

Bank 3:2 Busy (XFLASH)

These bits indicate that a write operation is running on the corresponding Bank of

XFLASH. They are automatically set when bit WMS is set. Setting Protection

operation sets bit BSY2 (since protection registers are in the Block B2). When these

bits are set every read access to the corresponding Bank will output invalid data

(software trap 009Bh), while every write access to the Bank will be ignored. At the end

of the write operation or during a Program or Erase Suspend these bits are

automatically reset and the Bank returns to read mode. After a Program or Erase

Resume these bits are automatically set again.

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