ST10F276 datasheet(170/229 Pages) STMICROELECTRONICS

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ST10F276

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Note:

BTYP (bit 6 and 7) is set according to the configuration of the bit l6 and l7 of PORT0 latched

at the end of the reset sequence.

BUSCON0 is initialized with 0000h, if EA pin is high during reset. If EA pin is low during

reset, bit BUSACT0 and ALECTRL0 are set (‘1’) and bit field BTYP is loaded with the bus

configuration selected via PORT0.

RP0H (F108h / 84h)

ESFR

Reset value: --XXh

987

65432

CLKSEL

SALSEL

CSSEL

WRC

Table 79.

RPOH description(1)

RP0H is a read-only register.

Bit

Function

WRC (2)

Write configuration control

‘0’: Pin WR acts as WRL, pin BHE acts as WRH

‘1’: Pins WR and BHE retain their normal function

CSSEL (2)

Chip select line selection (number of active CS outputs)

0 0: 3 CS lines: CS2...CS0

0 1: 2 CS lines: CS1...CS0

1 0: No CS line at all

1 1: 5 CS lines: CS4...CS0 (Default without pull-downs)

SALSEL (2)

These bits are set according to Port 0 configuration during any reset sequence.

Segment address line selection (number of active segment address outputs)

’00’: 4-bit segment address: A19...A16

’01’: No segment address lines at all

’10’: 8-bit segment address: A23...A16

’11’: 2-bit segment address: A17...A16 (Default without pull-downs)

CLKSEL(2) (3)

RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on

each Port P0H pins during reset, RP0H default value is “FFh”.

System clock selection

’000’: fCPU = 16 x fOSC

’001’: fCPU = 0.5 x fOSC

’010’: fCPU = 10 x fOSC

’011’: fCPU = fOSC

’100’: fCPU = 5 x fOSC

’101’: fCPU = 8 x fOSC

’110’: fCPU = 3 x fOSC

’111’: fCPU = 4 x fOSC

EXICON (F1C0h / E0h)

ESFR

Reset value: 0000h

987

65432

EXI7ES

EXI6ES

EXI5ES

EXI4ES

EXI3ES

EXI2ES

EXI1ES

EXI0ES

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