ST10F276 datasheet(172/229 Pages) STMICROELECTRONICS

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ST10F276

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Table 83.

SFR area description

Bit

Function

GLVL

Group level

Defines the internal order for simultaneous requests of the same priority.

’3’: Highest group priority

’0’: Lowest group priority

ILVL

Interrupt priority level

Defines the priority level for the arbitration of requests.

’Fh’: Highest priority level

’0h’: Lowest priority level

xxIE

Interrupt enable control bit (individually enables/disables a specific source)

‘0’: Interrupt request is disabled

‘1’: Interrupt request is enabled

xxIR

Interrupt request flag

‘0’: No request pending

‘1’: This source has raised an interrupt request

XPERCON (F024h / 12h)

ESFR

Reset value:- 005h

987

65432

---

XMISC

XI2C

XSSC

XASC

XPWM

XFLAS

HEN

XRTC

XRAM2

XRAM1

CAN2

CAN1

Table 84.

ESFR description

Bit

Function

CAN1EN

CAN1 enable bit

‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled (P4.5

and P4.6 pins can be used as general purpose I/Os, but address range 00’EC00h-

00’EFFFh is directed to external memory only if CAN2EN, XRTCEN, XASCEN,

XSSCEN, XI2CEN, XPWMEN an XMISCEN are ‘0’ also).

‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.

CAN2EN

CAN2 enable bit

‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled (P4.4

and P4.7 pins can be used as general purpose I/Os, but address range 00’EC00h-

00’EFFFh is directed to external memory only if CAN1EN, XRTCEN, XASCEN,

XSSCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also).

‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.

XRAM1EN

XRAM1 enable bit

‘0’: Accesses to the on-chip 2 Kbyte XRAM are disabled. Address range

00’E000h-00’E7FFh is directed to external memory.

‘1’: The on-chip 2 Kbyte XRAM is enabled and can be accessed.

XRAM2EN

XRAM2 enable bit

‘0’: Accesses to the on-chip 64 Kbyte XRAM are disabled, external access

performed. Address range 0F’0000h-0F’FFFFh is directed to external memory

only if XFLASHEN is ‘0’ also.

‘1’: The on-chip 64 Kbyte XRAM is enabled and can be accessed.

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