PCF2131 datasheet(52/85 Pages) NXP

52 / 85 page

NXP Semiconductors

PCF2131

Nano-power highly accurate RTC with integrated quartz crystal

[1]

The chip enable must not be wired permanently LOW.

7.16.1.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a whole byte, with the Most

Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal SDA/CE. The first byte transmitted is the

command byte. Subsequent bytes are either data to be written or data to be read (see Figure 26).

SDO

aaa-041579

SDA/CE

DATA

SDI

COMMAND

DATA

Figure 26. Data transfer overview

The command byte defines the address of the first register to be accessed and the read/write mode. The

address counter will auto increment after every access and will reset to zero after the last valid register is

accessed. The R/W bit defines if the following bytes are read or write information.

Bit

Symbol

Value

Description

data read or write selection

write data

R/W

read data

6 to 0

00h to 36h

Table 86. Command byte definition

aaa-041580

seconds data 45BCD

minutes data 10BCD

addr 07h

R/W

SCL

SDI

SDA/CE

address

counter

In this example, the Seconds register is set to 45 seconds and the Minutes register to 10 minutes.

Figure 27. SPI-bus write example

PCF2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.0 — 5 October 2023

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