PCF2131 datasheet(40/85 Pages) NXP

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NXP Semiconductors

PCF2131

Nano-power highly accurate RTC with integrated quartz crystal

The timestamp function also depends on the control bit BTSE in register Control_3, see Section 7.12.4.

7.12.3 Timestamp registers

7.12.3.1 Register Timestp_ctl1/2/3/4

Bits labeled as T are unused and return 0 when read

Bit

Symbol

TSM

TSOFF

SUBSEC_TIMESTP[4:0]

Reset

value

Table 64. Timestp_ctl1/2/3/4 - timestamp control register (address 14h/1Bh/22h/29h) bit allocation

Bits labeled as T are unused and return 0 when read

Bit

Symbol

Value

Description

in subsequent events without clearing the timestamp

flags, the last event is stored

TSM

in subsequent events without clearing the timestamp

flags, the first event is stored

timestamp function active

TSOFF

timestamp function disabled

unused

4 to 0

SUBSEC_TIMESTP[4:0]

1⁄16 second timestamp information coded in BCD

format when 100TH_S_DIS = ‘1’[1], 1⁄20 second

timestamp information coded in BCD format when

100TH_S_DIS = ‘0’;

Table 65. Timestp_ctl1/2/3/4 - timestamp control register (address 14h/1Bh/22h/29h) bit description

[1]

The time recorded in the time stamps, when in 100 Hz disable mode (1 Hz mode), will be at least two 16 Hz clocks behind the timestamp event and no

more than 3 clocks behind. If the exact time of the timestamp event is required then subtract 2 subseconds from the timestamp value and the result will

have -0 subseconds to +1 subseconds of uncertainty.

7.12.3.2 Register Sec_timestp

Bits labeled as T are unused and return 0 when read

Bit

Symbol

SECOND_TIMESTP (0 to 59)

Reset

value

Table 66. Sec_timestp1/2/3/4 - second timestamp register (address 15h/1Ch/23h/2Ah) bit allocation

PCF2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.0 — 5 October 2023

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