PCF2131 datasheet(47/85 Pages) NXP

47 / 85 page

NXP Semiconductors

PCF2131

Nano-power highly accurate RTC with integrated quartz crystal

aaa-041574

minute counter

minute alarm

INTA/B

SCL

instruction

CLEAR INSTRUCTION

8th clock

Example where only the minute alarm is used and no other interrupts are enabled.

Figure 21. AF timing diagram

7.13.5 Timestamp interrupts

Interrupt generation from the timestamp function is controlled using the TSIE1-4 bit (register Control_5). If

TSIE1-4 is enabled, the INTA/B pin follows the status of the flags TSF1/2/3/4, if not masked. Clearing the flags

TSFx immediately clears INTA/B. No pulse generation is possible for timestamp interrupts.

7.13.6 Battery switch-over interrupts

Generation of interrupts from the battery switch-over is controlled by the BIE bit (register Control_3). If BIE is

enabled, the INTA/B pin follows the status of bit BF in register Control_3 if not masked(see Table 78). Clearing

BF immediately clears INTA/B. No pulse generation is possible for battery switch-over interrupts.

7.13.7 Battery low detection interrupts

Generation of interrupts from the battery low detection is controlled by the BLIE bit (register Control_3). If BLIE

is enabled, the INTA/B pin follows the status of bit BLF (register Control_3) if not masked. The interrupt is

cleared when the battery is replaced (BLF is logic 0) or when bit BLIE is disabled (BLIE is logic 0). BLF is read

only and therefore cannot be cleared by command.

7.13.8 Interrupt masks

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

INT_A/B_MASK1

Reset

value

Table 80. INT_A/B_MASK1 - interrupt mask 1 register (address 31h/33h) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

Value

Description

7 to 6

unused

Table 81. INT_A/B_MASK1 - interrupt mask 1 register (address 31h/33h) bit description

PCF2131

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Product data sheet

Rev. 2.0 — 5 October 2023

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