PCF2131 datasheet(44/85 Pages) NXP

44 / 85 page

NXP Semiconductors

PCF2131

Nano-power highly accurate RTC with integrated quartz crystal

The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the interrupts generated from

the second/minute timer (flag MSF in register Control_2) are pulsed signals or a permanently active signal.

All the other interrupt sources generate a permanently active interrupt signal which follows the status of the

corresponding flags. When the interrupt sources are all disabled, INTA/B remains high-impedance.

• The flags MSF, AF, TSFx, and BF can be cleared by command.

• The flag WDTF is read only. How it can be cleared is explained in Section 7.11.5.

• The flag BLF is read only. It is cleared automatically from the battery low detection circuit when the battery is

replaced.

aaa-041571

BLF: BATTERY

LOW FLAG

SET

set battery

low flag, BLF

to interface:

read BLF

BLIE

from battery

low detection

circuit: clear BF

CLEAR

BF: BATTERY

FLAG

SET

set battery

flag, BF

to interface:

read BF

BIE

from interface:

clear BF

CLEAR

TSF1/2/3/4:

TIMESTAMP FLAGS

SET

set timestamp

flag, TSF1/2/3/4

to interface:

read TSF1/2/3/4_x

TSIE1/2/3/4

from interface:

clear TSF

CLEAR

AF: ALARM

FLAG

SET

set alarm

flag, AF

to interface:

read AF

AIE

from interface:

clear AF

CLEAR

WDTF:

WATCHDOG

TIMER FLAG

SET

WATCHDOG

COUNTER

to interface:

read WD_CD

WD_CD

MCU loading

watchdog counter

CLEAR

INTA pin

MSF:

MINUTE

SECOND FLAG

SET

MINUTES COUNTER

SECONDS COUNTER

to interface:

read MSF

SI/MI

TI_TP

from interface:

clear MSF

CLEAR

PULSE

GENERATOR 1

TRIGGER

CLEAR

BLIEA

BIEA

TSIE1/2/3/4A

AIEA

WD_CDA

SIA/MIA

BLIEB

BIEB

TSIE1/2/3/4B

AIEB

WD_CDB

SIB/MIB

INTB pin

When SI, MI, WD_CD, AIE, TSIE1/2/3/4, BIE, BLIE are all disabled, INTA/INTB remains high-impedance.

Figure 17. Interrupt block diagram

7.13.1 Minute and second interrupts

Minute and second interrupts are generated by predefined timers. The timers can be enabled independently

from one another by the bits MI and SI in register Control_1. However, a minute interrupt enabled on top of a

second interrupt cannot be distinguishable since it occurs at the same time.

The minute/second flag MSF (register Control_2) is set logic 1 when either the seconds or the minutes counter

increments according to the enabled interrupt (see Table 79). The MSF flag can be cleared by command.

PCF2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.0 — 5 October 2023

44 / 85

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