PCF2131 datasheet(23/85 Pages) NXP

23 / 85 page

NXP Semiconductors

PCF2131

Nano-power highly accurate RTC with integrated quartz crystal

depending on temperature and supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set

(OSF set logic 1).

The OTP refresh (see Section 7.3.2) should ideally be executed as the first instruction after start-up and also

after a reset due to an oscillator stop.

aaa-015298

chip in reset

chip not in reset

chip fully operative

VDD

oscillation

internal

reset

OTPR

CLKOUT

available

Figure 9. Dependency between POR and oscillator

After POR, the following mode is entered:

• 32.768 kHz CLKOUT active

• Power-On Reset Override (PORO) available to be set

• 24-hour mode is selected

• Battery switch-over function disabled, only one power supply (VDD)

• Temperature compensation enabled

• 100th second enabled

• Time 00:00:00.00

• Date 2001.01.01

• Weekday Monday

The register values after power-on are shown in Table 4.

7.7.2 Power-On Reset Override (PORO)

The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times

experienced by these types of circuits, a mechanism has been built in to disable the POR and therefore speed

up the on-board test of the device.

001aaj324

OSCILLATOR

0 = override inactive

1 = override active

0 = clear override mode

1 = override possible

POR_OVRD

SDA/CE

SCL

RESET

OVERRIDE

CLEAR

osc stopped

0 = stopped, 1 = running

reset

Figure 10. Power-On Reset (POR) system

PCF2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.0 — 5 October 2023

23 / 85

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