PCF2131 datasheet(50/85 Pages) NXP

50 / 85 page

NXP Semiconductors

PCF2131

Nano-power highly accurate RTC with integrated quartz crystal

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OSCILLATOR

OSCILLATOR STOP

DETECTOR

setting the OS flag

div 4

32768 Hz

8192 Hz

stop

PRESCALER

RESET

100 Hz tick

1 Hz tick

CPR

Figure 22. CPR and STOP bit functional diagram

The stop signal blocks the 8.192 kHz clock from generating system clocks and freezes the time. In this state,

the prescaler can be cleared with the CPR command in the Resets register.

Remark: The CLKOUT output of clock frequencies is not affected.

The time circuits can then be set and do not increment until the STOP bit is released. There is a slight chance

that STOP is set during a carry over of multiple time registers, which may have been executed incomplete.

Therefore time must be set before clearing STOP to maintain time integrity.

The stop acts on the 8.192 kHz signal. Because the I2C-bus or TS pin input is asynchronous to the crystal

oscillator, the accuracy of restarting the time circuits is between zero and one 8.192 kHz cycle (see Figure 23).

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0 µs to 122 µs

8192 Hz

stop released

Figure 23. STOP release timing

The first increment of the time circuits is between 0 s and 122 µs after STOP is released.

7.16 Interfaces

The PCF2131 has an I2C-bus or SPI-bus interface using the same pins. The selection is done using the

interface selection pin IFS (see Table 84).

Connection

Bus interface

Reference

VSS

SPI-bus

Section 7.16.1

IFS

VDD

I2C-bus

Section 7.16.2

Table 84. Interface selection input pin IFS

PCF2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.0 — 5 October 2023

50 / 85

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