Datasheet

14

002-37178 Rev. *B

2023-10-10

EZ-PD™ PAG2S-PS integrated USB PD and

synchronous-rectification controller

Functional description

3.1.1

SR_SEN false negative sense detection

The SR sense block monitors for the negative sense detect to turn on SR_GRDV. There is a chance of a false

negative sense detect during secondary resonance. To avoid this, EZ-PD™ PAG2S-PS implements a proprietary

voltage-second balance mechanism. In this mechanism, the SR block does an integral of the SR_SEN voltage

once it crosses the VBUS level and compares this voltage against an internal reference. Figure 7 shows that the

negative sense is considered valid only when the SR_SEN integral voltage crosses the reference voltage. The

reference voltage is firmware configurable and can be modified as needed based on system parameters.

Figure 7

SR_SEN negative sense detection

Time

Primary Current

Secondary Current

SR_SEN

Primary FET ON,

SR FET OFF

Primary FET OFF,

SR FET ON

True Negative sense

ZCD

Both FET OFF

SR_SEN Integral

Voltage

VREF

False Negative sense

VBUS Level