Datasheet

9

002-37178 Rev. *B

2023-10-10

EZ-PD™ PAG2S-PS integrated USB PD and

synchronous-rectification controller

Pinouts

2.2

Pin description

2.2.1

SR_GDRV, SR_VSS, SR_SEN, SR_CPP, SR_CPN, SR_CAP

EZ-PD™ PAG2S-PS senses the voltage across the synchronous rectifier NFET and appropriately controls the gate

driver to achieve optimum efficiency, it supports both standard NFET and logic level NFET. EZ-PD™ PAG2S-PS

supports synchronous rectification in QR/CrCM, valley switching, discontinuous conduction mode (DCM), and

continuous conduction mode (CCM). The SR sense block supports negative sense detect and ZCD. For CCM mode,

fast detection of SR_DRAIN crossing 0 V is done via SR_CAP pin by coupling SR_DRAIN to SR_CAP via a 10 pF

capacitor.

The gate driver (SR_GDRV) can be driven to internal VDDD or twice VDDD to achieve lower RDS-On of the external

NFET. The Gate Driver can be driven to twice of VDDD using an internal doubler circuit, with the doubler capacitor

connected across SR_CPP and SR_CPN pins. The source terminal of the SR FET shall be connected to the SR_VSS

pin. SR block implements an adaptive voltage doubler, wherein the voltage doubler feature is enabled or

disabled on-the-fly based on the SR_GDRV pulse width and a configurable firmware parameter. The voltage at

the drain node of the external NFET is sensed via SR_SEN using a resistive divider.

2.2.2

FB, EA_OUT, CC_COMP_GPIOx

EZ-PD™ PAG2S-PS integrates two error amplifier blocks that handle secondary output sensing and feedback for

both constant voltage and constant current modes of operation. The error amplifier output can be used to

regulate the current drawn through the external optocoupler. The negative input of the error amplifier is the

feedback (FB) pin and the positive input is an internal voltage reference. Based on the desired VBUS output, the

voltage at the FB pin will be varied using internal current source/sink IDACs. An external compensation network

is required between the FB pin and EA_OUT pin, as shown in the application diagram (see Figure 1). The constant

current operation makes use of an internal low-side current sense amplifier (LSCSA), the output of which feeds

into an independent error amplifier as shown in the functional block diagram. Constant current mode regulation

requires an external compensation network between CC_COMP_GPIOx and EA_OUT as shown in Figure 1.

EZ-PD™ PAG2S-PS error amplifier can ensure constant voltage regulation from 3.3 V to 28 V range and constant

current regulation from 1 A to 5 A as required by the USB PD PPS EPR specification.

2.2.3

VBUS_IN, VDDD, VCCD

EZ-PD™ PAG2S-PS integrates a high-voltage regulator, which is powered from the VBUS_IN rail, the output of the

regulator powers the VDDD rail. The input to the regulator can range from 3.3 V minimum to 30 V maximum. This

regulator is intended to deliver EZ-PD™ PAG2S-PS current consumption and is not expected to drive any external

loads or ICs. EZ-PD™ PAG2S-PS also has an internal configurable discharge path for the VBUS_IN rail, which is

used to discharge the VBUS rail during negative voltage transitions. The discharge resistor strength is

configurable through firmware settings.

The regulated supply VDDD is either used to directly power some internal analog blocks or further regulated

down to 1.8 V VCCD, which powers the majority of the core. VDDD and VCCD are brought out onto pins to connect

external capacitors for regulator stability and these are not meant to be used as power supplies.

2.2.4

VBUS_C, VBUS_CTRL

VBUS_C is used to monitor the voltage at the Type-C connector. VBUS_C has an internal configurable discharge

path, which is used to discharge the VBUS_C rail during negative voltage transitions. The discharge resistor

strength is configurable through firmware settings. The load switch is between VBUS_IN and VBUS_C.

EZ-PD™ PAG2S-PS integrates an NFET gate driver to control this load switch. VBUS_CTRL is the output of this gate

driver. There is an optional slow turn-on feature which is meant to avoid the sudden in-rush current.

2.2.5

CSP, CSN

EZ-PD™ PAG2S-PS integrates a low-side current sense amplifier (LSCSA) to monitor the load current. CSP is the

positive input pin for the LSCSA and CSN is the negative input. Suggested Rsense for LSCSA is 5 m.