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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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COM20022I-HT датащи(PDF) 65 Page - SMSC Corporation |
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COM20022I-HT датащи(HTML) 65 Page - SMSC Corporation |
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65 / 82 page  10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet SMSC COM20022I Page 65 Revision 02-27-06 DATASHEET A0-A2 VALID DATA VALID D0-D15 nCS t8 t1 t9 t3 t6 t4 t2 nDS DIR t5 t7 t10 t11 nIOCS16 t12 VALID VALUE t13 Note 2 Parameter min max units t1 t2 t3 t4 t5 t6 t7 15 10 5** 0 nS Address Setup to nDS Active Address Hold from nDS Inactive nCS Setup to nDS Active nCS Hold from nDS Inactive DIR Setup to nDS Active Cycle Time (nDS Low to Next Time Low) DIR Hold from nDS Inactive 4TARB * nS nS nS nS nS nS t8 nS nDS Low to Valid Data 40** t9 t10 t11 t12 t13 nS nS nS nS nS nDS High to Data High Impedence nDS Low Width nDS High Width nIOCS16 Output Delay from nCS Low nIOCS16 Hold Delay from nCS High 20 10 10 0 60 20 CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0 0**** 40*** The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. Note 1: nCS may become active after control becomes active, but the access time (t8) will now be 45nS measured from the leading edge of nCS. ** *** t12 is measured from the latest active (valid) timing among nCS, A0-A2. TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 * TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2. **** Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle |
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