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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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COM20022I-HT датащи(PDF) 61 Page - SMSC Corporation |
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COM20022I-HT датащи(HTML) 61 Page - SMSC Corporation |
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61 / 82 page  10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet SMSC COM20022I Page 61 Revision 02-27-06 DATASHEET Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals Write Cycle AD0-AD2, VALID nCS t1 t3 t8 ALE VALID DATA t2, t6 t5 t4 t7 D3-D15 DIR t9 t10 Note 2 t8** nDS t11 t12 t13 t14 t16 nIOCS16 Previous Value Invalid Valid Value t15 Parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 20 10 10 10 15 10 4TARB * 10 10 20 20 20 20 0 nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nDS Low Valid Data Setup to nDS High Data Hold from nDS High DIR Setup to nDS Active DIR Hold from nDS Inactive 30 MUST BE: BUSTMG pin = HIGH ALE High Width ALE Low Width nDS Low Width nDS High Width nIOCS16 Hold Delay from ALE Low nIOCS16 Output Delay from ALE Low Cycle Time (nDS to Next )** 40 The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. Note 1: Any cycle occurring after a write to Address Pointer Low Register requires a minimum of 4TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2: ** TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 * TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. |
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