COM20022I-HT datasheet(4/82 Pages) SMSC

4 / 82 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

Revision 02-27-06

Page 4

SMSC COM20022I

DATASHEET

6.7

Command Chaining....................................................................................................................................51

6.7.1

Transmit Command Chaining .............................................................................................................51

6.7.2

Receive Command Chaining ..............................................................................................................52

6.8

Reset Details ..............................................................................................................................................53

6.8.1

Internal Reset Logic ............................................................................................................................53

6.9

Initialization Sequence ...............................................................................................................................53

6.9.1

Bus Determination...............................................................................................................................53

6.10

Improved Diagnostics .............................................................................................................................54

6.10.1

Normal Results: ...............................................................................................................................54

6.10.2

Abnormal Results: ...........................................................................................................................55

6.11

Oscillator.................................................................................................................................................55

Chapter 7

Operational Description........................................................................................................ 56

7.1

Maximum Guaranteed Ratings* .................................................................................................................56

7.2

DC Electrical Characteristics ......................................................................................................................56

Chapter 8

Timing Diagrams .................................................................................................................. 59

Chapter 9

Package Outline ................................................................................................................... 78

Chapter 10

Appendix A ........................................................................................................................... 79

10.1

NOSYNC Bit ...........................................................................................................................................79

10.2

EF Bit......................................................................................................................................................79

Chapter 11

Appendix B: Example of Interface Circuit Diagram to ISA Bus........................................... 82

List of Figures

Figure 2.1 - COM20022I Pin Configuration ....................................................................................................................7

Figure 3.1 - COM20022I Operation..............................................................................................................................10

Figure 5.1 - Multiplexed, 8051-Like Bus Interface with RS-485 Interface .......................................................................17

Figure 5.2 - Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ...............................................................18

Figure 5.3 - DREQ Pin First Assertion Timing for All DMA Modes ...............................................................................21

Figure 5.4 - Programmable Burst Mode DMA Transfer (Rough Timing) ......................................................................22

Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing.................................................................................23

Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing ........................................................................................23

Figure 5.7 - High Speed CPU Bus Timing - Intel CPU Mode .......................................................................................25

Figure 5.8 - COM20022I Network Using RS-485 Differential Transceivers ....................................................................27

Figure 5.9 - Dipulse Waveform for Data of 1-1-0 ...........................................................................................................27

Figure 5.10 - Internal Block Diagram.............................................................................................................................28

Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing................................................................................36

Figure 6.2 - Sequential Access Operation.....................................................................................................................46

Figure 6.3 - RAM Buffer Packet Configuration .............................................................................................................49

Figure 6.4 - Command Chaining Status Register Queue .............................................................................................51

Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle ........................................................................59

Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle ........................................................................60

Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals Write Cycle..........................................................................61

Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................62

Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................63

Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................64

Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................65

Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................66

Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle .................................................................67

Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle ...............................................................68

Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................69

Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................70

Figure 8.13 - Normal Mode Transmit or Receive Timing..............................................................................................71

Figure 8.14 - Backplane Mode Transmit or Receive Timing ........................................................................................72

Figure 8.15 - TTL Input Timing on XTAL1 Pin..............................................................................................................73

Figure 8.16 - Reset and Interrupt Timing .....................................................................................................................73

Figure 8.17 - DMA Timing (Intel Mode 80XX) ..............................................................................................................74

Figure 8.18 - DMA Timing (Motorola Mode 68XX) .......................................................................................................75

Figure 9.1 - COM20022I 48 Pin TQFP Package Outline..............................................................................................78

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