COM20022I-HT datasheet(63/82 Pages) SMSC

63 / 82 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 63

Revision 02-27-06

DATASHEET

Figure 8.5

- Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle

A0-A2

VALID DATA

VALID

D0-D15

nCS

nRD

nWR

t10

Note 3

nIOCS16

t11

VALID VALUE

t12

Note 2

Parameter

min

max

units

t10

t11

t12

5**

Address Setup to nRD Active

Address Hold from nRD Inactive

nCS Setup to nRD Active

nCS Hold from nRD Inactive

Cycle Time (nRD Low to Next Time Low)

nRD Low to Valid Data

nRD High to Data High Impedance

4TARB

40**

CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0

nRD Low Width

nRD High Width

nWR

to nRD Low

nIOCS16 Output Delay from nCS Low

nIOCS16 Hold Delay from nCS High

0****

40***

The Microcontroller typically accesses the COM20022 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20022 cycles.

Note 1:

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

nCS may become active after control becomes active, but the access time (t6)

will now be 45nS measured from the leading edge of nCS.

t11 is measured from the latest active (valid) timing among nCS, A0-A2.

***

t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.

****

Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from

Data Register requires a minimum of 5TARB from the trailing edge of nRD to the

leading edge of the next nRD.

Notes 2 and 3 are applied to an access to Data Register by DMA transfer.

Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to

Data Register requires a minimum of 5TARB from the trailing edge of nWR to the

leading edge of nRD.

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