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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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COM20022I-HT датащи(PDF) 32 Page - SMSC Corporation |
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COM20022I-HT датащи(HTML) 32 Page - SMSC Corporation |
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32 / 82 page  10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet Revision 02-27-06 Page 32 SMSC COM20022I DATASHEET Table 6.2 - Write Register Summary ADDR MSB WRITE LSB REGISTER 00 RI/TR1 0 0 DMA END EXCNAK RECON NEW NEXTID TA/ TTA INTERRUPT MASK 01 C7 C6 C5 C4 C3 C2 C1 C0 COMMAND 02 RD- DATA AUTO- INC 0 0 DMAEN A10 A9 A8 ADDRESS PTR HIGH 03 A7 A6 A5 A4 A3 A2 A1 A0/ SWAP ADDRESS PTR LOW 04 D7 D6 D5 D4 D3 D2 D1 D0 DATA* 05 (R/W)* 0 0 0 (R/W)* SUB- AD2 SUB- AD1 SUB- AD0 SUBADR 06 RESET CCHEN TXEN ET1 ET2 BACK- PLANE SUB- AD1 SUB- AD0 CONFIG- URATION 07-0 TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 TENTID 07-1 NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 NODEID 07-2 P1- MODE FOUR NAKS 0 RCV- ALL CKP3 CKP2 CKP1 SLOW- ARB SETUP1 07-3 0 0 0 0 0 0 0 0 TEST 07-4 RBUS- TMG 0 CKUP1 CKUP0 EF NO- SYNC RCN- TM1 RCN- TM0 SETUP2 07-5 W16 0 ITCEN/ RTRG TC8/ RSYN/ GTTM DMA- MD1 DMA- MD0 TC- POL DRQ- POL BUS CONTROL 07-6 TC7/ TIM7/ CYC7 TC6/ TIM6/ CYC6 TC5/ TIM5/ CYC5 TC4/ TIM4/ CYC4 TC3/ TIM3/ CYC3 TC2/ TIM2/ CYC2 TC1/ TIM1/ CYC1 TC0/ TIM0/ CYC0 DMA COUNT Note*: This bit can be written and read. *DATA REGISTER AT 16 BIT ACCESS REGISTER BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDR DATA D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 04 6.2 Internal Registers The COM20022I contains 16 internal registers. Table 6.1 and Table 6.2 illustrate the COM20022I register map. All undefined bits are read as undefined and must be written as logic "0". 6.2.1 Interrupt Mask Register (IMR) The COM20022I is capable of generating an interrupt signal when certain status bits become true. A write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits capable of generating an interrupt include the Receiver Inhibited bit, DMAEND bit (new to the COM20022I), New Next |
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