COM20019IP datasheet(60/81 Pages) SMSC

60 / 81 page

FIGURE 13 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE

DISCONTINUED DATASHEET

A0-A2

VALID DATA

VALID

D0-D7

nCS

nRD

nWR

t10

Note 3

Note 2

Parameter

min

max

units

t10

5**

Address Setup to nRD Active

Address Hold from nRD Inactive

nCS Setup to nRD Active

nCS Hold from nRD Inactive

Cycle Time (nRD Low to Next Time Low)

nRD Low to Valid Data

nRD High to Data High Impedance

4TARB

40**

CASE 1: RBUSTMG bit = 0

nRD Low Width

nRD High Width

nWR

to nRD Low

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. Same as the XTAL1 period.

nCS may become active after control becomes active, but the access time (t6)

will now be 45nS measured from the leading edge of nCS.

The Microcontroller typically accesses the COM20019 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20019 cycles.

Note 1:

Note 2:

Read cycle for Address Pointer Low/High Registers occurring after a read from

Data Register requires a minimum of 5TARB from the trailing edge of nRD to the

leading edge of the next nRD.

Note 3:

Read cycle for Address Pointer Low/High Registers occurring after a write to

Data Register requires a minimum of 5TARB rom the trailing edge of nWR to the

leading edge of nRD

COM20019IP датащи(PDF) 60 Page - SMSC Corporation

COM20019IP датащи(HTML) 60 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

датащи скачать

ссылки URL