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COM20019IP датащи(PDF) 32 Page - SMSC Corporation

номер детали COM20019IP
подробное описание детали  Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
PDF  81 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

COM20019IP датащи(HTML) 32 Page - SMSC Corporation

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DATA
COMMAND
DESCRIPTION
000r p110
Clear Flags
This command resets certain status bits of the COM20019. A
logic "1" on "p" resets the POR status bit and the EXCNAK
Diagnostic status bit. A logic "1" on "r" resets the RECON status
bit.
0000 1000
Clear
Receive
Interrupt
This command is used only in the Command Chaining operation.
Please refer to the Command Chaining section for definition of
this command.
Table 7 - Address Pointer High Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
7
Read Data
RDDATA
This bit tells the COM20019 whether the following access
will be a read or write. A logic "1" prepares the device for a
read, a logic "0" prepares it for a write.
6
Auto Increment
AUTOINC
This bit controls whether the address pointer will increment
automatically.
A logic "1" on this bit allows automatic
increment of the pointer after each access, while a logic "0"
disables this function.
Please refer to the Sequential
Access Memory section for further detail.
5-3
(Reserved)
These bits are undefined.
2-0
Address 10-8
A10-A8
These bits hold the upper three address bits which provide
addresses to RAM.
Table 8 - Address Pointer Low Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
7-0
Address 7-0
A7-A0
These bits hold the lower 8 address bits which provide the
addresses to RAM.



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