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COM20019IP датащи(PDF) 56 Page - SMSC Corporation

номер детали COM20019IP
подробное описание детали  Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
PDF  81 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

COM20019IP датащи(HTML) 56 Page - SMSC Corporation

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56
DISCONTINUED DATASHEET
AD0-AD2,
VALID
nCS
t1
t3
t8
VALID DATA
ALE
t2,
t6
t5
t4
t7
D3-D7
nRD
t9
t10
nWR
t11
t12
t13 Note 3
Note 2
MUST BE: RBUSTMG bit = 0
Parameter
min
max
units
t1
t2
t3
t4
t5
t6
t7
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nRD Low
nRD Low to Valid Data
nRD High to Data High Impedance
Cycle Time (nRD Low to Next Time Low)
20
10
10
10
15
0
4TARB
*
40
20
nS
nS
nS
nS
nS
nS
nS
20
20
60
20
20
ALE High Width
ALE Low Width
nRD Low Width
nRD High Width
nWR
to nRD Low
t8
t9
t10
t11
t12
t13
nS
nS
nS
nS
nS
nS
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Note 2:
Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3:
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.



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