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COM20019IP датащи(PDF) 54 Page - SMSC Corporation

номер детали COM20019IP
подробное описание детали  Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
PDF  81 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

COM20019IP датащи(HTML) 54 Page - SMSC Corporation

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TIMING DIAGRAMS
54
DISCONTINUED DATASHEET
AD0-AD2,
VALID
VALID DATA
nCS
t1
t3
t8
ALE
t2,
t6
t5
t4
t7
D3-D7
DIR
t9
t10
t11
t12
nDS
t13
t14
Note 2
Parameter
min
max
units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
nDS Low to Valid Data
nDS High to Data High Impedance
Cycle Time (nDS Low to Next Time Low)
DIR Setup to nDS Active
DIR Hold from nDS Inactive
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
20
10
10
10
15
0
4TARB
*
10
10
20
20
60
20
40
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
MUST BE: RBUSTMG bit = 0
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
Topr is the period of operation clock. Same as the XTAL1 period.
Note 2:
Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.



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