USB3250 datasheet(27/48 Pages) SMSC

27 / 48 page

USB2.0 PHY IC

Datasheet

SMSC GT3200, SMSC USB3250

Revision 1.5 (03-24-06)

DATASHEET

The behavior of the Transmit State Machine is described below.

Asserting a RESET forces the transmit state machine into the Reset state which negates

TXREADY. When RESET is negated the transmit state machine will enter a wait state.

The SIE asserts TXVALID to begin a transmission.

After the SIE asserts TXVALID it can assume that the transmission has started when it detects

TXREADY has been asserted.

The SIE must assume that the PHY has consumed a data byte if TXREADY and TXVALID are

asserted on the rising edge of CLKOUT.

The SIE must have valid packet information (PID) asserted on the TXDATA bus coincident with the

assertion of TXVALID.

TXREADY is sampled by the SIE on the rising edge of CLKOUT.

The SIE negates TXVALID to complete a packet. Once negated, the transmit logic will never

reassert TXREADY until after the EOP has been generated. (TXREADY will not re-assert until

TXVALID asserts again).

The PHY is ready to transmit another packet immediately, however the SIE must conform to the

minimum inter-packet delays identified in the USB2.0 specification.

7.5

RX Logic

This block receives serial data from the CRC block and processes it to be transferred to the SIE on

the RXDATA bus. The processing involved includes NRZI decoding, bit unstuffing, and serial to

parallel conversion. Upon valid assertion of the proper RX control lines by the RX State Machine, the

RX Logic block will provide bytes to the RXDATA bus as shown in the figures below. The behavior of

the Receive State Machine is described below.

Figure 7.6 Transmit Timing for 16-bit Data, Odd Byte Count

CLK30

DATA[7:0]

TXREADY

TXVALID

DP/DM

PID

DATA

SYNC

DATA

CRC

PID

DATA[15:8]

DATA (0)

DATA (1)

DATA (2)

DATA (3)

CRC(HI)

CRC (LO)

VALIDH

EOP

USB3250 датащи(PDF) 27 Page - SMSC Corporation

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