USB3250 datasheet(25/48 Pages) SMSC

25 / 48 page

USB2.0 PHY IC

Datasheet

SMSC GT3200, SMSC USB3250

Revision 1.5 (03-24-06)

DATASHEET

Figure 7.2 shows the relationship between CLK60 and the transmit data transfer signals in FS mode.

TXREADY is only asserted for one CLK60 per byte time to signal the SIE that the data on the TXDATA

lines has been read by the Macrocell. The SIE may hold the data on the TXDATA lines for the duration

of the byte time. Transitions of TXVALID must meet the defined setup and hold times relative to

CLK60.

Figure 7.3 shows the relationship between CLK60 and the receive data control signals in FS mode.

RXACTIVE "frames" a packet, transitioning only at the beginning and end of a packet. However

transitions of RXVALID may take place any time 8 bits of data are available. Figure 7.3 also shows

how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be

presented for the full byte time. The XCVRSELECT signal determines whether the HS or FS timing

relationship is applied to the data and control signals.

7.3

Clock and Data Recovery Circuit

This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer. The Elasticity

Buffer is used to compensate for differences between the transmitting and receiving clock domains.

The USB2.0 specification defines a maximum clock error of ±1000ppm of drift.

Figure 7.2 FS CLK Relationship to Transmit Data and Control Signals (8-bit mode)

Figure 7.3 FS CLK Relationship to Receive Data and Control Signals (8-bit mode)

CLKOUT

TXDATA[7:0]

TXVALID

TXREADY

Don't

Care

DATA3

PID

DATA4

DATA1

DATA2

DATA(n+1)

DATA(n+2)

CLK60

RXACTIVE

RXDATA[7:0]

RXVALID

DATA(n)

USB3250 датащи(PDF) 25 Page - SMSC Corporation