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AT43USB326 датащи(PDF) 32 Page - ATMEL Corporation |
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AT43USB326 датащи(HTML) 32 Page - ATMEL Corporation |
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32 / 102 page ![]() 32 AT43USB326 3313D–USB–04/06 USB Interrupt Enable Register – UIER • Bit 7 – SOF IE: Enable Start of Frame Interrupt When the SOF IE bit is set (1), the Start of Frame Interrupt is enabled. • Bit 6 – EOF2 IE: Enable EOF2 Interrupt When the EOF2 IE bit is set (1), the EOF2 Interrupt is enabled. • Bit 5, 4 – Res: Reserved Bits These bits are reserved and always read as zero. • Bit 3 – HEP0 IE: Enable Endpoint 0 Interrupt When the HEP0 IE bit is set (1), the Hub Endpoint 0 Interrupt is enabled. • Bit 2 – FEP2 IE: Enable Endpoint 2 Interrupt When the FE2 IE bit is set (1), the Function Endpoint 2 Interrupt is enabled. • Bit 1 – FEP1 IE: Enable Endpoint 1 Interrupt When the FE1 IE bit is set (1), the Function Endpoint 1 Interrupt is enabled. • Bit 0 – FEP0 IE: Enable Endpoint 0 Interrupt When the FE0 IE bit is set (1), the Function Endpoint 0 Interrupt is enabled. Suspend/Resume Register – SPRSR • Bit 7..3 – Res: Reserved Bits These bits are reserved and are always read as zeros. • Bit 2 – FRWUP: Function Remote Wakeup The USB hardware sets this bit to signal that External Interrupt 1 is detected indicating remote wakeup. An interrupt is generated if the FRWUP IE bit of the SPRSIE register is set. • Bit 1 – RSM: Resume The USB hardware sets this bit when a USB resume signaling is detected at any of its port except Port 1. An interrupt is generated if the RSM IE bit of the SPRSIE register is set. • Bit 0 – GLB SUSP: Global Suspend The USB hardware sets this bit when a USB global suspend signaling is detected. An interrupt is generated if the GLBSUSP IE bit of the SPRSIE register is set. Bit 7 6 5 4 3 2 1 0 $1FF3 SOF IE EOF2 IE – – HEP0 IE FEP2 IE FEP1 IE FEP0 IE UIER Read/Write R/W R/W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 543 2 1 0 $1FFA – – – – – FRWUP RSM GLB SUSP SPRSR Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 |
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