AT43USB326 datasheet(22/102 Pages) ATMEL

22 / 102 page

AT43USB326

3313D–USB–04/06

External Reset

An external reset is generated by a low-level on the RESET pin. Reset pulses longer than

200 ns will generate a reset. Shorter pulses are not guaranteed to generate a reset. When the

applied signal reaches the Reset Threshold Voltage - V

RST on its positive edge, the delay timer

starts the MCU after the Time-out period t

TOUT has expired.

Figure 7. External Reset During Operation

Watchdog Timer

Reset

When the watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT.

Figure 8. Watchdog Reset During Operation

Non-USB Related

Interrupt Handling

The AT43USB326 has two non-USB 8-bit Interrupt Mask control registers; GIMSK (General

Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register).

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts

are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is

set (one) when a Return from Interrupt instruction, RETI, is executed.

For Interrupts triggered by events that can remain static (e.g. the Output Compare register1

matching the value of Timer/Counter1) the interrupt flag is set when the event occurs. If the

interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the

event occurs the next time.

When the Program Counter is vectored to the actual interrupt vector in order to execute the

interrupt handling routine, hard-ware clears the corresponding flag that generated the inter-

rupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag bit

position(s) to be cleared.

tTOUT

VRST

VCC

RESET

TIME-OUT

INTERNAL

RESET

tTOUT

VCC

RESET

WDT

TIME-OUT

RESET

TIME-OUT

1 XTAL Cycle

INTERNAL

RESET

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