5

SPI timing specification

This section specifies the SPI control interface used to control data transfer.

The communication interface is based on a 4-wire, serial, synchronous interface between the host (controller) and

the VL53L8CH (target device). Refer to the schematics in Section 2.6 Application schematics. The 4-wire

interface comprises the following four signals:

•

NCS: Chip select (active low)

•

MCLK: Main serial clock

•

MOSI: Main output secondary input, data output from controller

•

MISO: Main input secondary output, data output from target

All signals are CMOS inputs/outputs. Their levels are in line with the IOVDD supply. The SPI modes supported

are clock polarity = 1 and clock phase = 1. These modes correspond to data captured on a clock’s rising edge

and data propagated on a falling edge. The controller selects the target device with the NCS. The NCS enables

target transmission. It is an active low signal. After the device is selected with the falling edge of the NCS, an 8-bit

command can be received. If the VL53L8CH has not been activated using the NCS chip select line, the MCLK

input clock and MOSI signals are disregarded.

The falling edge (high to low transition) of the NCS signal is required to initiate an action. The transmission ends

with the rising edge (low-to-high transition). This causes the end of data transfer, and resets the internal counter

and command registers. All this reinitializes the serial communication.

While the register address is applied on the MOSI pin, the same information is mirrored on the MISO pin.

The NCS can be reset to a noncommunication state (high) at any time, including during a transaction. Should this

happen, the device resets its internal state machine. Consequently, any ongoing communications are aborted. No

internal changes to the registers occur, and the interface is ready to receive a new transaction again. However,

the SPI target can tolerate the MCLK being interrupted. It can resume at any point in time, without specific

duration limit.

During each SPI clock cycle, a full duplex data transmission occurs. The MOSI input is the data signal, provided

by the host to the device. It carries both the address and data information in write mode. Only address information

is in read mode. The controller sends a bit on the MOSI line and the target reads it. Concurrently, the target sends

a bit on the MISO line and the controller reads it. This sequence is maintained even when only one-directional

data transfer is intended.

The MISO output is the data signal, provided by the device to the host. It carries the data in read mode only, and

the mode register content during the address setup. Any internal register that can be written to, can also be read

from. There are also read-only registers that contain device status information. For example, design revision

details. A read instruction from an unused register location returns the value 0x00. A read instruction from the

manufacturer’s specific registers may return any value. A write instruction to a reserved or unused register

location is illegal. The effect of such a write is ignored. Transmission may continue for any number of clock cycles.

When complete, the controller stops toggling the clock signal, and typically deselects the target.

VL53L8CH

SPI timing specification

DS14310 - Rev 3

page 16/44