ADFS7124-4BBCPZ datasheet(91/93 Pages) AD

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Data Sheet

ADFS7124-4

ON-CHIP REGISTERS

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Rev. 0 | 91 of 93

FILTER REGISTERS

RS[5:0] = 1, 0, 0, 0, 0, 1 to 1, 0, 1, 0, 0, 0

Power-On/Reset = 0x060180

The ADFS7124-4 has eight filter registers, FILTER_0 to FILTER_7. Each filter register is associated with a setup; FILTER_x is associated with

Setup x. In the filter register, the filter type and output word rate are set.

Table 75 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Filter (0)

REJ60 (0)

POST_FILTER (0)

SINGLE_CYCLE (0)

0 (0)

FS[10:8] (0)

FS[7:0] (0)

Table 75. Filter Register Bit Descriptions

Bits

Bit Name

Description

23:21

Filter

Filter type select bits. These bits select the filter type.

000 = sinc4 filter (default).

001 = reserved.

010 = sinc3 filter.

011 = reserved.

100 = fast settling filter using the sinc4 filter. The sinc4 filter is followed by an averaging block, which results in a settling time equal to

the conversion time. In full power and mid power modes, averaging by 16 occurs whereas averaging by 8 occurs in low power mode.

101 = fast settling filter using the sinc3 filter. The sinc3 filter is followed by an averaging block, which results in a settling time equal to

the conversion time. In full power and mid power modes, averaging by 16 occurs whereas averaging by 8 occurs in low power mode.

110 = reserved.

111 = post filter enabled. The ADFS7124-4 includes several post filters, selectable using the POST_FILTER bits. The post filters have

single cycle settling, the settling time being considerably better than a simple sinc3/sinc4 filter. These filters offer excellent 50 Hz and

60 Hz rejection.

REJ60

When this bit is set, a first order notch is placed at 60 Hz when the first notch of the sinc filter is at 50 Hz. This allows simultaneous 50

Hz and 60 Hz rejection.

19:17

POST_FILTER

Post filter type select bits. When the filter bits are set to 1, the sinc3 filter is followed by a post filter which offers good 50 Hz and 60 Hz

rejection at output data rates that have zero latency approximately.

POST_FILTER

Output Data Rate (SPS)

Rejection at 50 Hz and 60 Hz ± 1 Hz (dB)

000

Reserved

Not applicable

001

Reserved

Not applicable

010

27.27

011

100

Reserved

Not applicable

101

110

16.7

111

Reserved

Not applicable

SINGLE_CYCLE

Single cycle conversion enable bit. When this bit is set, the ADFS7124-4 settles in one conversion cycle so that it functions as a zero

latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected.

When the fast filters are used, this bit has no effect.

15:11

These bits must be programmed with a Logic 0 for correct operation.

10:0

FS[10:0]

Filter output data rate select bits. These bits set the output data rate of the sinc3 and sinc4 filters as well as the fast settling filters.

In addition, they affect the position of the first notch of the filter and the cutoff frequency. In association with the gain selection, they

also determine the output noise and, therefore, the effective resolution of the device (see noise tables). FS can have a value from 1 to

2047.

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