ADFS7124-4BBCPZ datasheet(88/93 Pages) AD

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Data Sheet

ADFS7124-4

ON-CHIP REGISTERS

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Rev. 0 | 88 of 93

MCLK_COUNT REGISTER

RS[5:0] = 0, 0, 1, 0, 0, 0

Power-On/Reset = 0x00

The controller clock frequency can be monitored using this register.

Table 72 outlines the bit designations for the register. Bit 7 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MCLK_COUNT (0)

Table 72. MCLK_COUNT Register Bit Descriptions

Bits

Bit Name

Description

7:0

MCLK_COUNT

This register allows the user to determine the frequency of the internal/external oscillator. Internally, a clock counter increments every 131

pulses of the sampling clock (614.4 kHz in the full power mode, 153.6 kHz in the mid power mode, and 768 kHz in the low power mode). The

8-bit counter wraps around on reaching its maximum value. The counter output is read back through this register. Note that the incrementation

of the register is asynchronous to the register read. If a register read coincides with the register incrementation, it is possible to read an invalid

value. To prevent this, read the register four times, then read the register four times again at a later point. By reading four values, it is possible

to identify the correct register value at the start and end of the timing instants.

CHANNEL REGISTERS

RS[5:0] = 0, 0, 1, 0, 0, 1 to 0, 1, 1, 0, 0, 0

Power-On/Reset = 0x8001 for CHANNEL_0; all other channel registers are set to 0x0001

Sixteen channel registers are included on the ADFS7124-4, CHANNEL_0 to CHANNEL_15. The channel registers begin at Address 0x09

(CHANNEL_0) and end at Address 0x18 (CHANNEL_15). Through each register, configure the channel (AINP input and AINM input), enable

or disable the channel, and select the setup. The setup is selectable from eight different options. When the ADC converts, it automatically

sequences through all enabled channels. This allows the user to sample some channels multiple times in a sequence, if required. In addition, it

allows the user to include diagnostic functions in a sequence also.

Table 73 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Enable (1)

Setup (0)

0 (0)

AINP[4:3](00)

AINP[2:0](000)

AINM[4:0](00001)

Table 73. Channel Register Bit Descriptions

Bits

Bit Name

Description

Enable

Channel enable bit. Setting this bit enables the device channel for the conversion sequence. By default, only the enable bit for Channel 0

is set. The order of conversions starts with the lowest enabled channel, then cycles through successively higher channel numbers, before

wrapping around to the lowest channel again.

When the ADC writes a result for a particular channel, the four LSBs of the status register are set to the channel number, 0 to 15. This allows

the channel the data corresponds to be identified. When the DATA_STATUS bit in the ADC_CONTROL register is set, the contents of the

status register are appended to each conversion when it is read. Use this function when several channels are enabled to determine to which

channel the conversion value read corresponds.

14:12

Setup

Setup select. These bits identify which of the eight setups are used to configure the ADC for this channel. A setup comprises a set of four

registers: analog configuration, output data rate/filter selection, offset register, and gain register. All channels can use the same setup, in

which case the same 3-bit value must be written to these bits on all active channels. Alternatively, up to eight channels can be configured

differently.

11:10

These bits must be programmed with a Logic 0 for correct operation.

9:5

AINP[4:0]

Positive analog input AINP input select. These bits select which of the analog inputs is connected to the positive input for this channel.

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