ADFS7124-4BBCPZ datasheet(87/93 Pages) AD

87 / 93 page

Data Sheet

ADFS7124-4

ON-CHIP REGISTERS

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Rev. 0 | 87 of 93

Table 71. ERROR_EN Register Bit Descriptions (Continued)

Bits

Bit Name

Description

source, the MCLK counter monitors this external clock. Similarly, if the on-chip oscillator is selected as the clock source to

the ADC, the MCLK counter monitors the on-chip oscillator.

LDO_CAP_CHK_TEST_EN

Test of analog/digital LDO decoupling capacitor check. When this bit is set, the decoupling capacitor is internally

disconnected from the LDO, forcing a fault condition. This allows the user to test the circuitry which is used for the analog

and digital LDO decoupling capacitor check.

20:19

LDO_CAP_CHK

Analog/digital LDO decoupling capacitor check. These bits enable the capacitor check. When a check is enabled, the ADC

checks for the presence of the external decoupling capacitor on the selected supply. When the check is complete, the

LDO_CAP_CHK bits are both reset to 0. Note that a missing decoupling capacitor can cause the ADC to reset. However,

this is easily detectable at the system level.

00 = check is not enabled.

01 = check the analog LDO capacitor.

10 = check the digital LDO capacitor.

11 = check is not enabled.

ADC_CAL_ERR_EN

When this bit is set, the calibration fail check is enabled.

ADC_CONV_ERR_EN

When this bit is set, the conversions are monitored and the ADC_CONV_ERR bit is set when a conversion fails.

ADC_SAT_ERR_EN

When this bit is set, the ADC modulator saturation check is enabled.

AINP_OV_ERR_EN

When this bit is set, the overvoltage monitor on all enabled AINP channels is enabled.

AINP_UV_ERR_EN

When this bit is set, the undervoltage monitor on all enabled AINP channels is enabled.

AINM_OV_ERR_EN

When this bit is set, the overvoltage monitor on all enabled AINM channels is enabled.

AINM_UV_ERR_EN

When this bit is set, the undervoltage monitor on all enabled AINM channels is enabled.

REF_DET_ERR_EN

When this bit is set, any external reference being used by the ADC is continuously monitored. An error is flagged if the

external reference is open circuit or has a value of less than 0.7 V.

DLDO_PSM_TRIP_TEST_EN

Checks the test mechanism that monitors the digital LDO. When this bit is set, the input to the test circuit is tied to DGND

instead of the LDO output. Set the DLDO_PSM_ERR bit in the error register.

DLDO_PSM_ERR_ERR

When this bit is set, the digital LDO voltage is continuously monitored. The DLDO_PSM_ERR bit in the error register is set

if the voltage being output from the digital LDO is outside specification.

ALDO_PSM_TRIP_TEST_EN

Checks the test mechanism that monitors the analog LDO. When this bit is set, the input to the test circuit is tied to AVSS

instead of the LDO output. Set the ALDO_PSM_ERR bit in the error register.

ALDO_PSM_ERR_EN

When this bit is set, the analog LDO voltage is continuously monitored. The ALDO_PSM_ERR bit in the error register is set

if the voltage being output from the analog LDO is outside specification.

SPI_IGNORE_ERR_EN

During power-on reset and calibrations, the on-chip registers cannot be written to. User write instructions are ignored by

the ADC. Set this bit so that the SPI_IGNORE_ERR bit in the error register informs when write operations are ignored.

SPI_SCLK_CNT_ERR_EN

When this bit is set, the SCLK counter is enabled. All read and write operations to the ADC are multiples of eight bits.

For every serial communication, the SCLK counter counts the number of SCLK pulses. CS must be used to frame each

read and write operation. If the number of SCLK pulses used during a communication is not a multiple of eight, the

SPI_SCLK_CNT_ERR bit in the error register is set. For example, a glitch on the SCLK pin during a read or write operation

can be interpreted as an SCLK pulse. In this case, the SPI_SCLK_CNT_ERR bit is set as there is an excessive number of

SCLK pulses detected. CS_EN in the ADC_CONTROL register must be set to 1 when the SCLK counter function is being

used.

SPI_READ_ERR_EN

When this bit is set, the SPI_READ_ERR bit in the error register is set when an error occurs during a read operation. An

error occurs if there is an attempt to read from invalid addresses. CS_EN in the ADC_CONTROL register must be set to 1

when the SPI read check function is being used.

SPI_WRITE_ERR_EN

When this bit is set, the SPI_WRITE_ERR bit in the error register is set when an error occurs during a write operation.

An error occurs if there is an attempt to write to invalid addresses or write to read-only registers. CS_EN in the

ADC_CONTROL register must be set to 1 when the SPI write check function is being used.

SPI_CRC_ERR_EN

This bit enables a CRC check of all read and write operations. The SPI_CRC_ERR bit in the error register is set if the CRC

check fails. In addition, an 8-bit CRC word is appended to all data read from the ADFS7124-4.

MM_CRC_ERR_EN

When this bit is set, a CRC calculation is performed on the memory map each time that the registers are written to.

Following this, periodic CRC checks are performed on the on-chip registers. If the register contents have changed, the

MM_CRC_ERR bit is set.

ROM_CRC_ERR_EN

When this bit is set, a CRC calculation is performed on the ROM contents on power-on. If the ROM contents have

changed, the ROM_CRC_ERR bit is set.

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