ADFS7124-4BBCPZ datasheet(42/93 Pages) AD

42 / 93 page

Data Sheet

ADFS7124-4

GETTING STARTED

analog.com

Rev. 0 | 42 of 93

Diagnostics

The ERROR_EN register enables and disables the numerous diag-

nostics on the ADFS7124-4. By default, the SPI_IGNORE function

is enabled, which indicates inappropriate times to write to the

ADC (for example, during power-up and during a reset). Other

diagnostics include:

►

SPI read and write checks, which ensure that only valid registers

are accessed.

►

SCLK counter, which ensures that the correct number of SCLK

pulses are used.

►

SPI CRC

►

Memory map CRC

►

LDO checks

When a diagnostic is enabled, the corresponding flag is contained

in the error register. All enabled flags are OR’ed to control the ERR

flag in the status register. Thus, if an error occurs (for example, the

SPI CRC check detects an error), the relevant flag (for example,

the SPI_CRC_ERR flag) in the error register is set. The ERR flag

in the status register is also set. This is useful when the status

bits are appended to conversions. The ERR bit indicates if an error

occurred. Then read the error register for more details on the error

source.

The frequency of the on-chip oscillator can also be monitored on

the ADFS7124-4. The MCLK_COUNT register monitors the control-

ler clock pulses. Table 44 to Table 46 give more details on the

diagnostic registers. See the Diagnostics section for more details

on the diagnostics available.

ADC Control Register

The ADC control register configures the core peripherals for use by

the ADFS7124-4 and the mode for the digital interface. The power

mode (full power, mid power, or low power) is selected through

this register. Also, the mode of operation is selected, for example,

continuous conversion or single conversion. Also select the standby

and power-down modes, as well as any of the calibration modes.

In addition, this register contains the clock source select bits and in-

ternal reference enable bits. The reference select bits are contained

in the setup configuration registers (see the ADC Setups section for

more information).

The digital interface operation is also selected through the ADC

control register. This register allows the user to enable the data plus

status read and continuous read mode. For more details, see the

Digital Interface section. The details of this register are shown in

Table 47.

ADFS7124-4BBCPZ датащи(PDF) 42 Page - Analog Devices

ADFS7124-4BBCPZ датащи(HTML) 42 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

датащи скачать

ссылки URL