ADFS7124-4BBCPZ datasheet(37/93 Pages) AD

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Data Sheet

ADFS7124-4

GETTING STARTED

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Rev. 0 | 37 of 93

Serial Interface

The ADFS7124-4 has a 3-wire or 4-wire SPI. The on-chip registers

are accessed through the serial interface.

Clock

The device has an internal 614.4 kHz clock. Use either this clock

or an external clock as the clock source for the device. The internal

clock can also be made available on a pin if a clock source is

required for external circuitry.

Temperature Sensor

The on-chip temperature sensor monitors the die temperature.

Digital Outputs

The ADFS7124-4 has two general-purpose digital outputs. These

can be used for driving external circuitry. For example, an external

multiplexer can be controlled by these outputs.

Calibration

Both internal calibration and system calibration are included on

chip; therefore, there is the option of removing offset or gain errors

internal to the device only, or removing the offset or gain errors of

the complete end system.

Excitation Currents

The device contains two excitation currents which can be set

independently to 0.1 µA, 50 µA, 100 µA, 250 µA, 500 µA, 750 µA,

or 1 mA.

Bias Voltage

A bias voltage generator is included on chip so that signals from

thermocouples can be biased suitably. The bias voltage is set to

(AVDD − AVSS)/2 and can be made available on any input. It can

supply multiple channels.

Bridge Power Switch (PSW)

A low-side power switch allows the user to power down bridges

interfaced to the ADC.

Diagnostics

The ADFS7124-4 includes numerous diagnostic features such as:

►

Reference detection

►

Overvoltage/undervoltage detection

►

CRC on SPI communications

►

CRC on the memory map

►

SPI read/write checks

These diagnostics allow a high level of fault coverage in an applica-

tion.

POWER SUPPLIES

The ADFS7124-4 operates with an analog power supply voltage

from 2.7 V to 3.6 V in low or mid power mode and from 2.9 V to

3.6 V in full power mode. The device accepts a digital power supply

from 1.65 V to 3.6 V.

The device has two independent power supply pins: AVDD and

IOVDD.

►

AVDD is referred to AVSS. AVDD powers the internal analog

regulator that supplies the ADC.

►

IOVDD is referred to DGND. This supply sets the interface logic

levels on the SPI and powers an internal regulator for operation

of the digital processing.

Single Supply Operation (AVSS = DGND)

When the ADFS7124-4 is powered from a single supply connected

to AVDD, AVSS and DGND can be shorted together on one single

ground plane. With this setup, an external level shifting circuit is

required when using truly bipolar inputs to shift the common-mode

voltage. Recommended regulators include the ADP162, which has

a low quiescent current.

Split Supply Operation (AVSS ≠ DGND)

The ADFS7124-4 can operate with AVSS set to a negative voltage,

allowing true bipolar inputs to be applied. This allows a truly fully

differential input signal centered around 0 V to be applied to the

ADFS7124-4 without the need for an external level shifting circuit.

For example, with a 3.6 V split supply, AVDD = +1.8 V and AVSS

= −1.8 V. In this use case, the ADFS7124-4 internally level shifts

the signals, allowing the digital output to function between DGND

(nominally 0 V) and IOVDD.

When using a split supply for AVDD and AVSS, the absolute max-

imum ratings must be considered (see the Absolute Maximum

Ratings section). Ensure that IOVDD is set below 3.6 V to stay

within the absolute maximum ratings for the device.

DIGITAL COMMUNICATION

The ADFS7124-4 has a 3-wire or 4-wire SPI compatible with

QSPI™, MICROWIRE™, and DSPs. The interface operates in SPI

Mode 3 and can be operated with CS tied low. In SPI Mode 3,

SCLK idles high, the falling edge of SCLK is the drive edge, and the

rising edge of SCLK is the sample edge. This means that data is

clocked out on the falling/drive edge and data is clocked in on the

rising/sample edge.

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