ADFS7124-4BBCPZ datasheet(51/93 Pages) AD

51 / 93 page

Data Sheet

ADFS7124-4

ADC CIRCUIT INFORMATION

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Rev. 0 | 51 of 93

from the data register, DOUT/RDY goes high. The data register can

be read several times, if required, even when DOUT/RDY is high.

Do not read the ADC_CONTROL register close to the completion of

a conversion because the mode bits are being updated by the ADC

to indicate that the ADC is in the standby mode.

If several channels are enabled, the ADC automatically sequences

through the enabled channels and performs a conversion on each

channel. When a conversion is started, DOUT/RDY goes high and

remains high until a valid conversion is available and CS is low.

As soon as the conversion is available, DOUT/RDY goes low.

The ADC then selects the next channel and begins a conversion.

Read the present conversion while the next conversion is being

performed. As soon as the next conversion is complete, the data

to read the conversion. When the ADC has performed a single

conversion on each of the selected channels, it returns to the

standby mode.

If the DATA_STATUS bit in the ADC_CONTROL register is set

to 1, the contents of the status register are output along with

the conversion each time that the data read is performed. The

four LSBs of the status register indicate the channel to which the

conversion corresponds.

Continuous Conversion Mode

Continuous conversion is the default power-up mode. The

ADFS7124-4 converts continuously, and the RDY bit in the status

the DOUT/RDY line also goes low when a conversion is complete.

To read a conversion, write to the communications register, indicat-

ing that the next operation is a read of the data register. When

the data-word is read from the data register, DOUT/RDY goes

high. The user can read this register additional times, if required.

However, ensure that the data register is not being accessed at the

completion of the next conversion; otherwise the new conversion

word is lost.

When several channels are enabled, the ADC automatically se-

quences through the enabled channels, performing one conversion

on each channel. When all channels are converted, the sequence

starts again with the first channel. The channels are converted

in order from the lowest enabled channel to the highest enabled

channel. The data register is updated as soon as each conversion

is available. The DOUT/RDY pin pulses low each time a conversion

is available. Then read the conversion while the ADC converts the

next enabled channel.

If the DATA_STATUS bit in the ADC_CONTROL register is set to 1,

the contents of the status register, along with the conversion data,

are output each time the data register is read. The status register

indicates the channel to which the conversion corresponds.

Figure 78. Single Conversion Configuration

Figure 79. Continuous Conversion Configuration

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