MP2733 datasheet(19/51 Pages) MPSIND

19 / 51 page

MP2733

– 4.5A SW CHARGER WITH I2C CONTROL, NVDC POWER PATH, USB OTG

MP2733 Rev. 1.1

www.MonolithicPower.com

5/18/2023

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

OPERATION

The MP2733 is a highly integrated, 4.5A, switch-

mode battery charger IC with narrow voltage DC

(NVDC) power path management for single-cell

Li-ion or Li-polymer battery applications. The

device integrates a reverse blocking FET (Q1), a

high-side MOSFET (Q2), a low-side MOSFET

(Q3), and a battery FET (Q4) between the SYS

and BATT pins.

Power Supply

The

VREF pin’s voltage supplies the internal

bias circuits, as well as the high-side MOSFET

(HS-FET) and low-side MOSFET (LS-FET) gate

drive. The STAT pull-up rail can also be

connected to VREF. The VREF pin has an

internal LDO with two inputs. One input is from

IN, and the other is from a battery. IN and the

battery voltage are connected to the input of the

LDO via a P-channel MOSFET.

Figure 3 shows the VREF power supply circuit.

VREF

Control

LDO

BATT

Figure 3: VREF Power Supply Circuit

Device Start-Up from Input Source

When an input source is plugged in, the MP2733

qualifies the input source before start-up. The

input source must meet both of the following

requirements:

1. VIN > VBATT + VHDRM

2. VIN_UVLO < VIN < VIN_OVLO

If the input power source meets the conditions

above, a good input is detected, and the device

asserts an INT signal to the host. Then the

device detects the input source type via the

DP/DM pins. When DP/DM detection completes,

the status register bit (VIN_STAT) changes and

an INT pulse is sent to the host. Then the device

starts up the step-down converter.

NVDC Power Path Management

The MP2733 employs an NVDC power structure

with the battery FET, decoupling the system

from the battery and thus allowing separate

controls between the system and the battery.

The system is a priority during start-up, even if

the battery is deeply discharged or missing. If the

input power is available with a depleted battery,

the system voltage is regulated to the minimum

system voltage (VSYS_REG_MIN).

Figure 4 shows the NVDC power structure,

which is composed of a front-end, step-down

DC/DC converter and a battery FET placed

between the SYS and BATT pins.

DC/DC

BATFET

Battery

Input

System

Charger IC

Figure 4: NVDC Power Path Management

Structure

The DC/DC converter is a 1.35MHz, step-down

switching regulator that directly drives the

system load and charges the battery through the

battery FET.

The system regulates the voltage in the following

ways:

If the battery voltage (VBATT) drops below

VSYS_MIN, the system voltage is regulated at

VSYS_REG_MIN, which exceeds VSYS_MIN by

VTRACK. The battery FET works linearly to

charge the battery via a trickle charge, pre-

charge, or fast charge current, depending

on VBATT. VSYS_MIN can be set via REG04h,

bits[3:1], and VTRACK can be set via REG04h,

bit[0].

When VBATT exceeds VSYS_MIN + VBATT_GD

(60mV), the battery FET fully turns on, and

the voltage difference between the system

and the battery is the VDS of the BATTFET.

The charge current loop is implemented by

the DC/DC converter

’s PWM control.

If charging is suspended or completed (the

battery FET is off), the system voltage is

always regulated at its maximum value

(VSYS_MIN, VBATT) + VTRACK.

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