MP2733 datasheet(5/51 Pages) MPSIND

5 / 51 page

MP2733

– 4.5A SW CHARGER WITH I2C CONTROL, NVDC POWER PATH, USB OTG

MP2733 Rev. 1.1

www.MonolithicPower.com

5/18/2023

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

PIN FUNCTIONS

Pin #

Name

Type

Description

1, 26

I/O

Positive pin of the USB data line pair.

Power input of the IC.

Place a 1μF ceramic capacitor from IN to PGND, as close

as possible to the IC.

PMID

Internal power pin. Connect PMID to the drain of the reverse-blocking MOSFET

and the drain of the high-side MOSFET (HS-FET). Bypass PMID with a 10

μF

capacitor from PMID to PGND, placed as close as possible to the IC.

Switching node.

5, 6, 7

PGND

Power ground.

BST

Bootstrap pin. Connect a 47nF bootstrap capacitor between the BST and SW pins

to form a floating supply across the power switch driver. This drives the power

switch’s gate above the supply voltage.

STAT

Open-drain charge status output to indicate various charger operations.

Connect STAT to VREF using a 10k

Ω resistor.

INT

Open-drain interrupt output. The INT pin can send charging status and fault

interrupt signals to the host.

NTC

Temperature-sense input. Connect a negative temperature coefficient thermistor

to the NTC pin. Configure the hot and cold temperature windows with a resistor

divider connected from VNTC to NTC to AGND. Charging is suspended when the

NTC pin is out of range.

VNTC

Pull-up voltage bias. The VNTC pin is the pull-up voltage bias of the NTC

comparator resistive divider for both the feedback and the reference.

13, 14

VREF

PWM low-side driver output. C

onnect a 10μF ceramic capacitor from VREF to

AGND, placed as close as possible to the IC.

AGND

Analog ground.

SYS

System output. Connect a 22

μF ceramic capacitor from SYS to PGND, placed as

close as possible to the IC.

BATT

Battery positive terminal. Connect a 22

μF ceramic capacitor from BATT to PGND,

placed as close as possible to the IC.

-------

Active low charge enable pin. Battery charging is enabled when the

corresponding register is set to active and the CE

-------

pin is low.

19, 20

SCL

I2C interface clock.

Connect SCL to the logic rail through a 10kΩ resistor.

SDA

I/O

I2C interface data.

Connect SDA to the logic rail through a 10kΩ resistor.

DISC

Battery disconnection control pin. The DISC pin can be used for shipping mode

and system resetting.

OTG

Boost mode enable control pin. The On-The-Go (OTG) function is enabled via

the I2C. During boost operation, the OTG pin can go low to suspend boost operation.

ILIM

Configurable input current limit. To set the maximum input current limit, connect

a resistor from ILIM to ground. The actual input current limit is the lower value set

by the ILIM pin or the I2C.

I/O

Negative pin of the USB data line pair.

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