80221 datasheet(12/91 Pages) LSI

12 / 91 page

80220/80221

MD400159/E

On the receive side for 100 Mbps operation, the twisted

pair receiver receives incoming encoded and scrambled

MLT-3 data from the twisted pair cable, remove any high

frequency noise, equalizes the input signal to compensate

for the effects of the cable, qualifies the data with a squelch

algorithm, and converts the data from MLT-3 coded twisted

pair levels to internal digital levels.

The output of the

twisted pair receiver then goes to a clock and data recov-

ery block which recovers a clock from the incoming data,

uses the clock to latch in valid data into the device, and

converts the data back to NRZ format. The NRZ data is

then unscrambled and decoded by the 4B5B decoder and

descrambler, respectively, and outputted to an external

Ethernet controller by the controller interface.

10 Mbps operation is similar to the 100 Mbps operation

except, (1) there is no scrambler/descrambler, (2) the

encoder/decoder is Manchester instead of 4B5B, (3) the

data rate is 10 Mbps instead of 100 Mbps, and (4) the

twisted pair symbol data is two level Manchester instead

of ternary MLT-3.

The AutoNegotiation block automatically configures the

device for either 100Base-TX or 10Base-T, and for either

Full or Half Duplex. This configuration is based on the

capabilities selected for this device and the capabilities

detected from a remote device.

The Management Interface, (hereafter referred to as the

MI serial port), is a two pin bidirectional link through which

configuration inputs can be set and status outputs can be

read.

Each block plus the operating modes are described in

more detail in the following sections. Since the 80220/

80221 can operate either as a 100Base-TX or a 10Base-T

device, each of the following sections describes the perfor-

mance of the respective section in both the 100 and 10

Mbps modes.

3.2 DIFFERENCES BETWEEN 80220 AND 80221

The differences between the 80220 and 80221 are sum-

marized in Table 1. For more information on each of these

features, refer to the appropriate sections where these

features are described.

Table 1. 80220 vs. 80221

Feature

80220

80221

Package

44L PLCC

64L LQFP

# LED Outputs

External

Yes

100Base-T4

Interface

Repeater Mode

Yes

3.3 CONTROLLER INTERFACE

3.3.1 General

The 80220/80221 has two interfaces to an external con-

troller: Media Independent Interface (referred to as the

MII) and Five Bit interface (referred to as the FBI).

3.3.2 MII - 100 Mbps

The MII is a nibble wide packet data interface defined in

IEEE 802.3 and shown in Figure 3. The 80220/80221

meets all the MII requirements outlined in IEEE 802.3. The

80220/80221 can directly connect, without any external

logic, to any Ethernet controllers or other devices which

also complies with the IEEE 802.3 MII specifications. The

MII frame format is shown in Figure 3.

The MII consists of eighteen signals: four transmit data

bits (TXD[3:0]), transmit clock (TX_CLK), transmit enable

(TX_EN), transmit error (TX_ER), four receive data bits

(RXD[3:0]), receive clock (RX_CLK), carrier sense (CRS),

receive data valid (RX_DV), receive data error (RX_ER),

and collision (COL). The transmit and receive clocks

operate at 25 MHz in 100 Mbps mode.

On the transmit side, the TX_CLK output runs continu-

ously at 25 Mhz. When no data is to be transmitted, TX_EN

has to be deasserted. While TX_EN is deasserted, TX_ER

and TXD[3:0] are ignored and no data is clocked into the

device. When TX_EN is asserted on the rising edge of

TX_CLK, data on TXD[3:0] is clocked into the device on

rising edges of the TX_CLK output clock. TXD[3:0] input

data is nibble wide packet data whose format needs to be

the same as specified in IEEE 802.3 and shown in Figure

3. When all data on TXD[3:0] has been latched into the

device, TX_EN has to be deasserted on the rising edge of

TX_CLK.

TX_ER is also clocked in on rising edges of the TX_CLK

clock. TX_ER is a transmit error signal which, when

asserted, will substitute an error nibble in place of the

normal data nibble that was clocked in on TXD[3:0]. The

error nibble is defined to be the /H/ symbol which is defined

in IEEE 802.3 and shown in Table 2.

Since OSCIN input clock generates the TX_CLK output

clock, TXD[3:0], TX_EN, and TX_ER are also clocked in

on rising edges of OSCIN.

On the receive side, as long as a valid data packet is not

detected, CRS and RX_DV are deasserted and RXD[3:0]

is held low. When the start of packet is detected , CRS and

RX_DV are asserted on falling edge of RX_CLK. The

assertion of RX_DV indicates that valid data is clocked out

on RXD[3:0] on falling edges of the RX_CLK clock. The

RXD[3:0] data has the same frame structure as the TXD[3:0]

data and is specified in IEEE 802.3 and shown in Figure 3.

80221 датащи(PDF) 12 Page - LSI Computer Systems

80221 датащи(HTML) 12 Page - LSI Computer Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

датащи скачать

ссылки URL