80221 datasheet(52/91 Pages) LSI

52 / 91 page

80220/80221

MD400159/E

The FBI requires 16 signals between the 80220/80221 and

a repeater core. The FBI signal count to a repeater core

will be 16 multiplied by the number of ports, which can be

quite large. The signal count between the 80220/80221

and repeater core can be reduced by 8 per device by

sharing the receive output pins and using RX_EN to

enable only that port where CRS is asserted. Refer to the

Controller Interface section within the Applications section

for more details on RX_EN.

5.9.3 Clocks

Normally, transmit data over the MII/FBI is clocked into the

80220/80221 with edges from the output clock TX_CLK. It

may be desireable or necessary in some repeater applica-

tions to clock in the transmit data from a master clock from

the repeater core. This would require that transmit data be

clocked in on edges of an input clock. An input clock is

available for clocking in data on TXD with the OSCIN pin.

Notice from the timing diagrams that OSCIN generates

TX_CLK, and TXD data is clocked in on TX_CLK edges.

This means that TXD data is also clocked in on OSCIN

edges as well. Thus, an external clock driving the OSCIN

input can also be used as the clock for TXD.

5.10 SERIAL PORT

5.10.1 General

The 80220/80221 has a MI serial port to access the

devices's configuration inputs and read out the status

outputs.

Any external device that has a IEEE 802.3

compliant MI interface can connect directly to the 80220/

80221 without any glue logic, as shown in Figures 11-13.

As described earlier, the MI serial port consists of 8 lines:

MDC, MDIO, MDINT, and MDA[4:0]. However, only 2

lines, MDC and MDIO, are needed to shift data in and out;

MDINT and MDA[4:0] are not needed but are provided for

convenience only.

Note that the MDA[4:0] addresses are inverted inside the

80220/80221 before going to the MI serial port block. This

means that the MDA[4:0] pins would have to be pin

strapped to 11111 externally in order to successfully

match the MI physical address of 00000 on the PHYAD[4:0]

bits internally.

5.10.2 Polling vs. Interrupt

The status output bits can be monitored by either polling

the serial port or with interrupt.

If polling is used, the registers can be read at regular

intervals and the status bits can be checked against their

previous values to determine any changes. To make

polling simpler, all the registers can be accessed in a single

read or write cycle by setting the register address bits

REGAD[4:0] to 11111 and adding enough clocks to read-

out out all the bits, provided the multiple register access

feature has been enabled.

The interrupt feature offers the ability to detect changes in

the status output bits without register polling. Assertion of

interrupt indicates that one or more of the status output bits

has changed since the last read cycle. There are three

interrupt output indicators on the 80220/80221: (1) MDINT

pin, (2) INT bit in the MI serial port Status Output register,

and (3) interrupt pulse on MDIO. These interrupt signals

can be used by an external device to initiate a read cycle.

Then when an interrupt is detected, the individual registers

(or multiple registers) can be read out and the status bits

compared against their previous values to determine any

changes. After the interrupt its have been read out, the

interrupt signals are automatically deasserted. A mask

grammed for each application.

5.10.3 Multiple Register Access

If the MI serial port needs to be constantly polled in order

to monitor changes in status output bits, or if it is desired

that all registers be read or written in a singleserial port

access cycle, multiple register access mode can be used.

Multiple register access allows access to all registers in a

single MI serial port access cycle. When multiple register

access is enabled, then all the registers are read/written

when the register address REGAD[4:0]=11111.

This

eliminates the need to read or write registers individually.

Multiple register access mode is normally disabled but it

can be enabled by setting the multiple register access

enable bit in the MI serial port Configuration 2 register.

5.10.4 Serial Port Addressing

The device address for the MI serial port are selected by

tying the MDA[4:0] pins to the desired value. MDA[4:0]

share the same pins as the MDINT and PLED[3:0] out-

puts, respectively, as shown Figure 15a. At powerup or

reset, the output drivers are tristated for an interval called

the power-on reset time.

During the power-on reset

interval, the value on these pins is latched into the device,

inverted, and used as the MI serial port address. The LED

outputs are open drain with internal resistor pullup to VCC.

If an LED is desired on the LED outputs, then an LED and

resistor are tied to VCC as shown in Figures 15b. If a high

address is desired, then the LED to VCC automatically

makes the latched address value a high. If a low value for

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