80221 datasheet(53/91 Pages) LSI

53 / 91 page

80220/80221

4-53

MD400159/E

the address is desired, then a 50K resistor to GND must be

added as shown in Figure 15b.

If no LED's are needed on the LED outputs, the selection

of addresses can be done as shown in Figure 15c. If a high

address is desired, the pin should be left floating and the

internal pullup will pull the pin high during power-on reset

time and latch in a high address value. If a low address is

desired, then the MDINT and

PLED[3:0] output pins

should be tied either directly to GND or through an optional

50K resistor to GND.

PLED3 should always be tied

through a 50K resistor to GND since it has both pullup and

pulldown capability. The optional 50K resistor also allows

the MDINT and PLED[2:0] pins to be used as digital

outputs under normal conditions.

Note that the MDA[4:0] addresses are inverted inside the

80220/80221 before going to the MI serial port block. This

means that the MDA[4:0] pins would have to be pin

strapped to 11111 externally in order to successfully

match the MI physical address bits PHYAD[4:0]=00000

internally.

Figure 15. Serial Device Port Address Selection

5.11 LONG CABLE

IEEE 802.3 specifies that 10BaseT and 100BaseTX oper-

ate over twisted pair cable lengths of between 0-100

meters. The squelch levels can be reduced by 4.5 dB if the

receive level adjust bit is appropriately set in the MI serial

port Configuration 1 register, which will allow the 80220/

80221 to operate with up to 150 meters of twisted pair

cable. The equalizer is already designed to accommodate

between 0-125 meters of cable.

5.12 AUTOMATIC JAM

The 80220/80221 has an automatic JAM generation fea-

ture which automatically transmits a JAM packet when

receive activity is detected. This feature is primarily de-

signed to give the user a means to easily implement half

duplex flow control. In a typical application, a watermark

signal from a system FIFO or memory would be tied

directly to the JAM pin. When the system FIFO is nearly

full and more data is incoming from receiver, the device will

automatically transmit a JAM packet and create a collision

which will cause the far end device to backoff allowing time

for the system FIFO to empty itself.

The JAM generation feature requires that the RX_EN/JAM

pin be programmed for JAM.

This can be done by

appropriately setting the R/J configuration select bit in the

MI serial port Configuration 2 register.

5.13 OSCILLATOR

The 80220/80221 requires a 25 Mhz reference frequency

for internal signal generation. This 25 Mhz reference

frequency

can be generated by either connecting an

external 25 Mhz crystal between OSCIN and GND or by

applying an external 25 Mhz clock to OSCIN.

If the crystal oscillator is used, it needs only a crystal, and

no other external capacitors or other components are

required. The crystal must have the characteristics shown

in Table 24.

The crystal must be placed as close as

possible to OSCIN and GND pins so that parasitics on

OSCIN are kept to a minimum.

Table 24. Crystal Specifications

Parameter

Spec

Type

Parallel Resonant

Frequency

25 Mhz +/- 0.01%

Equivalent Series

25 ohms max

Resistance

Load Capacitance

18 pF typ

Case Capacitance

7 pF max

Power

1mW max

Dissipation

a.) OUTPUT DRIVER / INPUT ADDRESS CORRESPONDENCE

b.) SETTING ADDRESS WITH LEDs

500

50 K

HIGH

LOW

c.) SETTING ADDRESS WITHOUT LEDs

HIGH

LOW

FLOAT

PLED3

PLED2

PLED1

PLED0

MDINT

PLED3

PLED2

PLED1

PLED0

MDINT

PLED3

PLED2

PLED1

PLED0

PLED3

PLED2

PLED1

PLED0

MDA3

MDA2

MDA1

MDA0

PLED3

PLED2

PLED1

PLED0

MDINT

MDA4

MDINT

(OPT)

MDINT

50K

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