80221 datasheet(28/91 Pages) LSI

28 / 91 page

80220/80221

MD400159/E

on reset interval, the value on these pins is latched into the

device, inverted, and used as the MI serial port physical

device addresses.

3.26.2 Timing

A timing diagram for a MI serial port frame is shown in

Figure 9. The MI serial port is idle when at least 32

continuous 1's are detected on MDIO and remains idle as

long as continuous 1's are detected. During idle, MDIO is

in the high impedance state. When the MI serial port is in

the idle state, a 01 pattern on the MDIO pin initiates a serial

shift cycle. Data on MDIO is then shifted in on the next 14

rising edges of MDC (MDIO is high impedance). If the

edges of MDC, data is either shifted in or out on MDIO,

depending on whether a write or read cycle was selected

with the bits READ and WRITE. After the 32 MDC cycles

have been completed, one complete register has been

read/written, the serial shift process is halted, data is

latched into the device, and MDIO goes into high imped-

ance state. Another serial shift cycle cannot be initiated

until the idle condition (at least 32 continuous 1's) is

detected.

3.26.3 Multiple Register Access

Multiple registers can be accessed on a single MI serial

port access cycle with the multiple register access feature.

The multiple register access feature can be enabled by

setting the multiple register access enable bit in the MI

serial port Configuration 2 register. When multiple register

access is enabled, multiple registers can be accessed on

a single MI serial port access cycle by setting the register

address to 11111 during the first 16 MDC clock cycles.

There is no actual register residing in register address

location 11111, so when the register address is then set to

11111, all eleven registers are accessed on the 176 rising

edges of MDC that occur after the first 16 MDC clock

cycles of the MI serial port access cycle. The registers are

accessed in numerical order from 0 to 20. After all 192

MDC clocks have been completed, all the registers have

been read/written, and the serial shift process is halted,

data is latched into the device, and MDIO goes into high

impedance state. Another serial shift cycle cannot be

initiated until the idle condition (at least 32 continuous 1's)

is detected.

3.26.4 Bit Types

Since the serial port is bidirectional, there are many types

of bits. Write bits (W) are inputs during a write cycle and are

high impedance during a read cycle. Read bits (R) are

outputs during a read cycle and high impedance during a

write cycle. Read/Write bits (R/W) are actually write bits

which can be read out during a read cycle. R/WSC bits are

R/W bits that are self clearing after a set period of time or

after a specific event has completed. R/LL bits are read

bits that latch themselves when they go low, and they stay

latched low until read. After they are read, they are reset

high. R/LH bits are the same as R/LL bits except that they

latch high.

R/LT are read bits that latch themselves

whenever they make a transition or change value, and

they stay latched until they are read. After R/LT bits are

read, they are updated to their current value. R/LT bits can

also be programmed to assert the interrupt function as

described in the Interrupt section. The bit type definitions

are summarized in Table 7.

Table 7. MI Register Bit Type Definition

Sym.

Name

Definition

Write Cycle

Read Cycle

Write

Input

No Operation, Hi Z

Read

No Operation,

Output

Hi Z

R/W

Read/

Input

Ouput

Write

R/WS

Read/

Input

Ouput

Write Self

Clearing

Clears Itself

After Operation

Completed

R/LL

Read/

No Operation,

Output

Latching

Hi Z

Low

When Bit Goes

Low, Bit Latched.

When Bit Is Read,

Bit Updated.

R/LH

Read/

No Operation,

Output

Latching

Hi Z

High

When Bit Goes

High, Bit Latched.

When Bit Is Read,

Bit Updated.

R/LT

Read/

No Operation,

Output

Latching

Hi Z

When Bit

Transition

Transitions,

Bit Latched And

Interrupt Set

When Bit Is Read,

Interrupt Cleared

And Bit Updated.

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