80221 datasheet(41/91 Pages) LSI

41 / 91 page

80220/80221

4-41

MD400159/E

Table 17. MI Register 17 (Configuration 2) Structure And Bit Definition

17.15

17.14

17.13

17.12

17.11

17.10

17.9

17.8

PLED3_1

PLED3_0

PLED2_1

PLED2_0

PLED1_1

PLED1_0

PLED0_1

PLED0_0

R/W

17.7

17.6

17.5

17.4

17.3

17.2

17.1

17.0

LED_DEF1

LED_DEF0

APOL_DIS

JAB_DIS

MREG

INT_MDIO

P26_CFG

R/W

Bit

Symbol

Name

Definition

R/W

Def.

17.15

PLED3_1

Programmable LED

11 = Normal

(PLED3 Is Determined By

R/W

17.14

PLED3_0

Output Select, Pin

Bits 17.7-17.6 And Table 5.

PLED3

Default is LINK100)

10 = LED Blink

(PLED3 Is Toggling 100 mS

Low, 100 mS High)

01 = LED On

(PLED3 Is Low)

00 = LED Off

(PLED3 Is High)

17.13

PLED2_1

Programmable LED

11 = Normal

(PLED2 Is Determined By

R/W

17.12

PLED2_0

Output Select, Pin

Bits 17.7-17.6 And Table 5.

PLED2

Default is Activity)

10 = LED Blink

(PLED2 Is Toggling 100 mS

Low, 100 mS High)

01 = LED On

(PLED2 Is Low)

00 = LED Off

(PLED2 Is High)

17.11

PLED1_1

Programmable LED

11 = Normal

(PLED1 Is Determined By

R/W

17.10

PLED1_0

Output Select, Pin

Bits 17.7-17.6 And Table 5.

PLED1

Default is Full Duplex)

10 = LED Blink

(PLED1 Is Toggling 100 mS

Low, 100 mS High)

01 = LED On

(PLED1 Is Low)

00 = LED Off

(PLED1 Is High)

17.9

PLED0_1

Programmable LED

11 = Normal

(PLED0 Is Determined By

R/W

17.8

PLED0_0

Output Select, Pin

Bits 17.7-17.6 And Table 5.

PLED0

Default is LINK10)

10 = LED Blink

(PLED0 Is Toggling 100 mS

Low, 100 mS High)

01 = LED On

(PLED0 Is Low)

00 = LED Off

(PLED0 Is High)

17.7

LED_DEF1

LED Normal

See Table 5

R/W

17.6

LED_DEF0

Function Select

17.5

APOL_DIS

Auto Polarity

1 = Auto Polarity Correction Function Disabled

R/W

Disable

0 = Normal

17.4

JAB_DIS

Jabber Disable

1 = Jabber Disabled

R/W

Select

0 = Enabled

17.3

MREG

Multiple Register

1 = Multiple Register Access Enabled

R/W

Access Enable

0 = No Multiple Register Access

17.2

INT_MDIO

Interrupt Scheme

1 = Interrupt Signaled With MDIO Pulse During Idle

R/W

Select

0 = Interrupt Not Signalled On MDIO

17.1

R/J_CFG

R/J Configuration

1 = RX_EN/JAM Pin Is Configured To Be JAM

R/W

Select

0 = RX_EN/JAM Pin Is Configured To Be RX_EN

17.0

Reserved

R/W

80221 датащи(PDF) 41 Page - LSI Computer Systems

80221 датащи(HTML) 41 Page - LSI Computer Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

датащи скачать

ссылки URL