CS5535 datasheet(139/555 Pages) NSC

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LPC Port Functional Description (Continued)

4.13.3 Serial IRQ

The LPC supports a serial IRQ scheme. This allows a sin-

gle signal to be used to report ISA-style interrupt requests.

Because more than one device may need to share the sin-

gle serial IRQ signal, an Open Collector signaling scheme

is used.

Serial interrupt information is transferred using three types

of frames: a Start frame, one or more IRQ Data frames,

and one Stop frame (see Figure Figure 4-42, Figure 4-43,

and Figure 4-44 on page 140). There are also two modes

of operation. Quiet mode, initiated by the peripheral, and

Continuous mode, initiated by the host:

Quiet (Active) Mode: To indicate an interrupt, the

peripheral brings the SERIRQ signal active for one

clock, and then places the signal in TRI-STATE mode.

This brings all the state machines from the Idle state to

the Active state.

The host then takes control of the SERIRQ signal by

driving it low on the next clock, and continues driving it

low for 3-7 clocks more (programmable). Thus, the

total number of clocks low will be 4-8. After those

clocks, the host drives SERIRQ high for one clock and

then places SERIRQ into the TRI-STATE mode.

Continuous (Idle) Mode: In this mode, the host ini-

tiates the Start frame, rather than the peripherals. Typ-

ically,

this

done

update

IRQ

status

(acknowledges). The host drives SERIRQ low for 4-8

clocks. This is the default mode after reset; it can be

used to enter the Quiet Mode.

Data Frame

Once the Start frame has been initiated, all of the serial

interrupt peripherals must start counting frames based on

the rising edge of the SERIRQ. Each of the IRQ/DATA

frames has exactly three phases of one clock each: a Sam-

ple phase, a Recovery phase, and a Turn Around phase.

During the sample phase, the device drives SERIRQ low if

the corresponding interrupt signals should be active. If the

corresponding interrupt is inactive, then the devices should

not drive the SERIRQ signal. It will remain high due to pull-

up registers. During the other two phases (Turn Around

and Recovery), no device should drive the SERIRQ signal.

The IRQ/DATA frames have a specific order and usage as

shown in Table 4-26.

Stop Frame

After all of the Data frames, a Stop frame is performed by

the host. This is accomplished by driving SERIRQ low for

two to three clocks. The number of clocks determines the

next mode:

• If the SERIRQ is low for two clocks, the next mode is the

Quiet mode. Any device may initiate a Start frame in the

second clock (or more) after the rising edge of the Stop

frame.

• If SERIRQ is low for three clocks, the next cycle is the

Continuous mode. Only the host may initiate a Start

frame in the second clock (or more) after the rising edge

of the Stop frame.

Table 4-26. IRQ Data Frames

Date Frame Number

Usage

0IRQ0

1IRQ1

SMI# (Not Supported)

3IRQ3

4IRQ4

5IRQ5

6IRQ6

7IRQ7

8IRQ8

9IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IOCHK#

INTA#

INTB#

INTC#

INTD#

31-21

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