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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS5535 датащи(PDF) 143 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 143 Page - National Semiconductor (TI) |
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143 / 555 page  Revision 0.8 143 www.national.com LPC Port Functional Description (Continued) Table 4-28. FWH Write Cycle Signal Clock Cycle LAD[3:0] Peripheral I/O Description START 1 1110b I On the rising edge of CLK with LFRAME# Low, the contents of LAD[3:0] indicate the start of an FWH cycle. IDSEL 1 0000 I Indicates which FWH peripheral is selected. The value on the LAD[3:0] is compared to the IDSEL strapping on the FWH device pins to select which device is being addressed. Note: From Intel(R) 82802 spec - the boot device must have an ID (determined by ID strapping Pins ID[3:0]) of 0. It is advisable that subsequent devices use incremental numbering. ADDR 7 xxxx I A 28-bit address phase is transferred starting with the most signifi- cant nibble first. MSIZE 1 0000b I Always 0000b (single byte transfer). DATA 2 xxxx I Data transfer is two cycles, starting with least significant nibble. TAR 1 1111b I The LPC host drives LAD[3:0] to 1111b to indicate a turnaround cycle. TAR 1 1111b (float) O The FWH device takes control of LAD[3:0] during this cycle. SYNC 1 0000b O The FWH device drives LAD[3:0] to 0000b to indicate it has received data or a command. TAR 1 1111b O The FWH device drives LAD[3:0] to 1111b, indicating a turnaround cycle. TAR 1 1111b (float) N/A The FWH device floats its output and the LPC host takes control of LAD[3:0]. |
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