CS5535 datasheet(138/555 Pages) NSC

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LPC Port Functional Description (Continued)

4.13.2.1 Host Initiated Cycles

Memory Cycles: Memory read or write cycles are

intended for memory-mapped devices. The ADDR field is a

full 32 bits, and transmitted with most significant nibble first.

Typically a memory device supports much less addressing

and ignores address bits above which it is capable of

decoding.

I/O Cycles: I/O read or write cycles are intended for

peripherals. These cycles are generally used for register or

FIFO accesses and have minimal Sync times. Data trans-

fers are assumed to be exactly 1 byte. The host is respon-

sible for breaking up larger data transfers into 8-bit cycles.

The minimum number of wait states between bytes is 1.

The host initiated cycles are shown in Table 4-24.

4.13.2.2 DMA Initiated Cycles

DMA on LPC is handled through the LDRQ# line from

peripherals and special encoding on LAD[3:0] for the host.

Single, demand, verify, and increment mode are supported

on the LPC interface. Block, decrement, and cascade are

not supported. Channels 0 through 3 are 8-bit channels.

Only 8-bit channels are supported.

Asserting DMA Requests: Peripherals need the DMA

service to encode their request channel number on the

LDRQ# signal. LDRQ# is synchronous with LCLK. Periph-

erals start the sequence by asserting LDRQ# low. The next

3 bits contain the encoded DMA channel number with the

MSB first. And the next bit (ACT) indicates whether the

requested channel is active or not. The case where the

ACT is low (inactive) will be rare, and is only used to indi-

cate that a previous request for that channel is being aban-

doned. After indication, LDRQ# should go high for at least

one clock. After that one clock LDRQ# can be brought low

for next encoding sequence (see Figure 4-41.)

DMA Transfer: Arbitration for DMA channels is performed

through the 8237 within the host. Once the host won the

arbitration, it asserts LFRAME# on the LPC bus. The host

starts a transfer by asserting 0000b on LAD[3:0] with

LFRAME# asserted. The host’s assert “cycle type” and

direction is based on the DMA transfer. In the next cycle it

asserts channel number and in the following cycle it indi-

cates the size of the transfer.

DMA Reads: The host drives 8 bits of data and turns the

bus around, then the peripheral acknowledges the data

with a valid SYNC.

DMA Writes: The host turns the bus around and waits for

data, then the peripheral indicates data is ready through

valid SYNC and transfer of the data.

The DMA initiated cycles are shown in Table 4-25.

Figure 4-41. DMA Cycle Timing Diagram

Table 4-24. Host Initiated Cycles

Memory or I/O

Driven By

Read Cycle

Write Cycle

START

Host

CYCTYP + DIR

Host

ADDR

Host

TAR

Host

SYNC

Peripheral

DATA

Peripheral

Host

TAR

Peripheral

Table 4-25. DMA Initiated Cycles

DMA

Driven By

Read Cycle

(Host to

Peripheral)

Write Cycle

(Peripheral to

Host)

START

Host

CYCTYP

Host

CHANNEL

Host

SIZE

Host

DATA

Host

TAR

Host

Peripheral

SYNC

Peripheral

TAR

Peripheral

START

MSB

LSB

ACT

START

LCLK

LDRQ#

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